公开(公告)号：US20250154000A1

公开(公告)日：2025-05-15

申请号：US19022673

申请日：2025-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei CHANG ,  Ya-Jen SHEUH ,  Ren-Dou LEE ,  Yi-Chih CHANG ,  Yi-Hsun CHIU ,  Yuan-Hsin CHI

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/66

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US20230068139A1

公开(公告)日：2023-03-02

申请号：US17459827

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei CHOU ,  Yuan-Hsin CHI ,  Yin-Tun CHOU ,  Hung-Chih WANG ,  Yu-Chi LIU ,  Chih-Ming WANG

IPC: H01L21/687 ,  H01L21/285 ,  H01L21/768

Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.

公开(公告)号：US20230383399A1

公开(公告)日：2023-11-30

申请号：US18446392

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Hsin-Lin WU ,  Yao-Fong DAI ,  Pei-Yuan TAI ,  Chin-Wei CHEN ,  Yin-Tun CHOU ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: C23C14/56 ,  H01L21/687 ,  C23C16/455 ,  C23C14/50

CPC classification number: C23C14/564 ,  H01L21/68735 ,  H01L21/68771 ,  C23C16/455 ,  C23C14/50

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US20220275500A1

公开(公告)日：2022-09-01

申请号：US17187410

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Hsin-Lin WU ,  Yao-Fong DAI ,  Pei-Yuan TAI ,  Chin-Wei CHEN ,  Yin-Tun CHOU ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: C23C14/56 ,  H01L21/687 ,  C23C14/50 ,  C23C16/455

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US20200172393A1

公开(公告)日：2020-06-04

申请号：US16695673

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei CHANG ,  Ya-Jen SHEUH ,  Ren-Dou LEE ,  Yi-Chih CHANG ,  Yi-Hsun CHIU ,  Yuan-Hsin CHI

IPC: B81C1/00 ,  H01L21/66 ,  H01L21/02 ,  H01L21/3105

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US20240387233A1

公开(公告)日：2024-11-21

申请号：US18786382

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei CHOU ,  Yuan-Hsin CHI ,  Yin-Tun CHOU ,  Hung-Chih WANG ,  Yu-Chi LIU ,  Chih-Ming WANG

IPC: H01L21/687 ,  H01L21/285 ,  H01L21/768

Abstract: A clamp ring including an inner periphery of increased diameter at locations where inwardly extending tabs are not located reduces the risk a workpiece that is placed in close proximity to the clamp ring or which contacts the clamp ring during processing will stick to the clamp ring.

公开(公告)号：US20240190701A1

公开(公告)日：2024-06-13

申请号：US18513545

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei CHANG ,  Ya-Jen SHEUH ,  Ren-Dou LEE ,  Yi-Chih CHANG ,  Yi-Hsun CHIU ,  Yuan-Hsin CHI

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/66

CPC classification number: B81C1/00238 ,  H01L21/02274 ,  H01L21/31053 ,  H01L22/12

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US20230375945A1

公开(公告)日：2023-11-23

申请号：US17749037

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Yao-Fong DAI ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: G03F7/20

CPC classification number: G03F7/70825 ,  H01L21/67742

Abstract: The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

公开(公告)号：US20230373100A1

公开(公告)日：2023-11-23

申请号：US17749051

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei CHOU ,  Sheng-Yuan LIN ,  Yuan-Hsin CHI ,  Hung-Chih WANG ,  Yu-Chi LIU

IPC: B25J15/00 ,  B25J11/00

CPC classification number: B25J15/0014 ,  B25J11/0095

Abstract: The present disclosure is directed to a transfer blade including a first end segment, a second end segment opposite to the first end segment, and an intermediate segment extending from the first end segment to the second end segment. The first end segment includes a first contact region and the second end segment includes a second contact region. The first and second contact regions are configured to contact locations of a surface of a workpiece that do not overlap or are not aligned with a sensitive area of the workpiece. The sensitive area of the workpiece may be an EUV frame or a reticle of the workpiece. A non-contact region extends continuously along the first end segment, the intermediate segment, and the second end segment, and the non-contact region overlaps the sensitive area of the workpiece and is spaced apart from the sensitive area of the workpiece.