公开(公告)号：US20170011925A1

公开(公告)日：2017-01-12

申请号：US14795751

申请日：2015-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang LIAO ,  Chia-Yao LIANG ,  Jui-Long CHEN ,  Sheng-Yuan LIN ,  Yi-Lii HUANG ,  Kuo-Hsi LEE ,  Po-An CHEN

IPC: H01L21/283 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3205 ,  H01L21/3213

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

Abstract translation: 半导体结构包括隔离结构，栅极堆叠，间隔物和图案化的抗蚀剂保护氧化物。 隔离结构形成在半导体衬底中，并且电隔离半导体衬底的器件区域。 栅极堆叠位于隔离结构上。 间隔件沿着隔离结构上的栅极堆叠的侧壁形成。 图案化的抗蚀剂保护氧化物位于隔离结构上并且覆盖间隔物的侧壁，使得间隔物置于图案化的抗蚀剂保护氧化物和栅极堆叠之间。

公开(公告)号：US20230383399A1

公开(公告)日：2023-11-30

申请号：US18446392

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Hsin-Lin WU ,  Yao-Fong DAI ,  Pei-Yuan TAI ,  Chin-Wei CHEN ,  Yin-Tun CHOU ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: C23C14/56 ,  H01L21/687 ,  C23C16/455 ,  C23C14/50

CPC classification number: C23C14/564 ,  H01L21/68735 ,  H01L21/68771 ,  C23C16/455 ,  C23C14/50

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US20220275500A1

公开(公告)日：2022-09-01

申请号：US17187410

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Hsin-Lin WU ,  Yao-Fong DAI ,  Pei-Yuan TAI ,  Chin-Wei CHEN ,  Yin-Tun CHOU ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: C23C14/56 ,  H01L21/687 ,  C23C14/50 ,  C23C16/455

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US20170229343A1

公开(公告)日：2017-08-10

申请号：US15495901

申请日：2017-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang LIAO ,  Chia-Yao LIANG ,  Jui-Long CHEN ,  Sheng-Yuan LIN ,  Yi-Lii HUANG ,  Kuo-Hsi LEE ,  Po-An CHEN

IPC: H01L21/768 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

公开(公告)号：US20230375945A1

公开(公告)日：2023-11-23

申请号：US17749037

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi SHEN ,  Yao-Fong DAI ,  Yuan-Hsin CHI ,  Sheng-Yuan LIN

IPC: G03F7/20

CPC classification number: G03F7/70825 ,  H01L21/67742

Abstract: The present disclosure is directed to workpiece support for supporting a workpiece during semiconductor processing. The workpiece support includes one or more support frame bodies including a plurality of spaced apart spacers on a first surface of the support frame bodies. The spacers include a first surface spaced apart from the first surface of the support frame body. The spacing between the first surface of the spacers and the first surface of the support frame body results in the underside of the workpiece contacting the spacers but not contacting the first surface of the support frame body. Portions of the underside of the workpiece that do not contact the first surface of the support frame body are less susceptible to damage or accumulation of unwanted debris.

公开(公告)号：US20230373100A1

公开(公告)日：2023-11-23

申请号：US17749051

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei CHOU ,  Sheng-Yuan LIN ,  Yuan-Hsin CHI ,  Hung-Chih WANG ,  Yu-Chi LIU

IPC: B25J15/00 ,  B25J11/00

CPC classification number: B25J15/0014 ,  B25J11/0095

Abstract: The present disclosure is directed to a transfer blade including a first end segment, a second end segment opposite to the first end segment, and an intermediate segment extending from the first end segment to the second end segment. The first end segment includes a first contact region and the second end segment includes a second contact region. The first and second contact regions are configured to contact locations of a surface of a workpiece that do not overlap or are not aligned with a sensitive area of the workpiece. The sensitive area of the workpiece may be an EUV frame or a reticle of the workpiece. A non-contact region extends continuously along the first end segment, the intermediate segment, and the second end segment, and the non-contact region overlaps the sensitive area of the workpiece and is spaced apart from the sensitive area of the workpiece.