公开(公告)号：US20220392796A1

公开(公告)日：2022-12-08

申请号：US17846431

申请日：2022-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chien-Chih CHEN ,  Yao-Min YU ,  Ching-Ling LEE ,  Ren-Dou LEE

IPC: H01L21/677 ,  H01L21/687 ,  B25J11/00

Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ⅖ of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ⅔ of a wafer thickness of the wafer.

公开(公告)号：US20240190701A1

公开(公告)日：2024-06-13

申请号：US18513545

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei CHANG ,  Ya-Jen SHEUH ,  Ren-Dou LEE ,  Yi-Chih CHANG ,  Yi-Hsun CHIU ,  Yuan-Hsin CHI

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/66

CPC classification number: B81C1/00238 ,  H01L21/02274 ,  H01L21/31053 ,  H01L22/12

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US20200339413A1

公开(公告)日：2020-10-29

申请号：US16927223

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jui CHEN ,  I-Shi WANG ,  Ren-Dou LEE ,  Jen-Hao LIU

IPC: B81B7/00 ,  B81C3/00 ,  B81B7/02 ,  B81C1/00

Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.

公开(公告)号：US20240383095A1

公开(公告)日：2024-11-21

申请号：US18786321

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung CHEN ,  Yi-Shao LIN ,  Sheng-Tai PENG ,  Ya-Jen SHEUH ,  Hung-Lin CHEN ,  Ren-Dou LEE

IPC: B24B37/20 ,  B24B37/013 ,  B24B37/04 ,  C09G1/02

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

公开(公告)号：US20200172393A1

公开(公告)日：2020-06-04

申请号：US16695673

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Wei CHANG ,  Ya-Jen SHEUH ,  Ren-Dou LEE ,  Yi-Chih CHANG ,  Yi-Hsun CHIU ,  Yuan-Hsin CHI

IPC: B81C1/00 ,  H01L21/66 ,  H01L21/02 ,  H01L21/3105

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

公开(公告)号：US20190066967A1

公开(公告)日：2019-02-28

申请号：US15692745

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Kun KAO ,  Tsung-Min LIN ,  Jen-Chung CHIU ,  Ren-Dou LEE

IPC: H01J37/08 ,  H01J37/317

Abstract: Ion generators for ion implanters are provided. The ion generator for an ion implanter includes an ion source arc chamber including an arc chamber housing and a thermal electron emitter coupled to the arc chamber housing. In addition, the thermal electron emitter includes a filament and a cathode, and the cathode has a solid top portion made of a work function modified conductive material including tungsten (W) and a work function modification metal.

公开(公告)号：US20160005694A1

公开(公告)日：2016-01-07

申请号：US14322495

申请日：2014-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Ying CHIEN ,  I-Shi WANG ,  Jen-Hao LIU ,  Ren-Dou LEE

IPC: H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2223/54426 ,  H01L2224/291 ,  H01L2224/32145 ,  H01L2224/83139 ,  H01L2224/83141 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2924/014

Abstract: A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion.

Abstract translation: 半导体封装结构包括第一晶片和第二晶片。 第一晶片具有凹部。 凹部具有底表面和邻近底表面的至少一个侧壁。 在底面和侧壁之间形成钝角。 第二晶片设置在第一晶片上并具有突出部分。 当突出部分进入凹部的开口时，突出部分沿着侧壁滑动到底面，使得突出部分联接到凹部。