-
公开(公告)号:US20200083333A1
公开(公告)日:2020-03-12
申请号:US16682897
申请日:2019-11-13
发明人: Che-Wei Yang , Hao-Hsiung Lin
IPC分类号: H01L29/24 , H01L21/8238 , H01L27/092 , H01L29/10
摘要: The current disclosure describes semiconductor devices, e.g., transistors including a thin semimetal layer as a channel region over a substrate, which includes bandgap opening and exhibits semiconductor properties. Described semiconductor devices include source/drain regions that include a thicker semimetal layer over the thin semimetal layer serving as the channel region, this thicker semimetal layer exhibiting metal properties. The semimetal used for the source/drain regions include a same or similar semimetal material as the semimetal of the channel region.
-
2.
公开(公告)号:US10516050B2
公开(公告)日:2019-12-24
申请号:US15454118
申请日:2017-03-09
发明人: Che-Wei Yang , Hao-Hsiung Lin , Samuel C. Pan
IPC分类号: H01L29/78 , H01L29/10 , H01L29/267 , H01L29/66 , H01L21/02 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/36
摘要: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.
-
公开(公告)号:US09711607B1
公开(公告)日:2017-07-18
申请号:US15130527
申请日:2016-04-15
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
CPC分类号: H01L29/42392 , H01L21/02444 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02636 , H01L21/02645 , H01L21/2018 , H01L27/1281 , H01L29/0673 , H01L29/66469 , H01L29/66477 , H01L29/775 , H01L29/78
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
-
公开(公告)号:US10957602B2
公开(公告)日:2021-03-23
申请号:US16712262
申请日:2019-12-12
发明人: Che-Wei Yang , Hao-Hsiung Lin , Samuel C. Pan
IPC分类号: H01L21/265 , H01L21/8234 , H01L29/10 , H01L29/66 , H01L29/417 , H01L29/78
摘要: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
-
公开(公告)号:US10832957B2
公开(公告)日:2020-11-10
申请号:US16712538
申请日:2019-12-12
发明人: Che-Wei Yang , Hao-Hsiung Lin , Samuel C. Pan
IPC分类号: H01L21/8234 , H01L29/10 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/265
摘要: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
-
公开(公告)号:US10510611B2
公开(公告)日:2019-12-17
申请号:US16502917
申请日:2019-07-03
发明人: Che-Wei Yang , Hao-Hsiung Lin , Samuel C. Pan
IPC分类号: H01L21/8234 , H01L29/10 , H01L29/78 , H01L29/417 , H01L29/66 , H01L21/265
摘要: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
-
公开(公告)号:US10134865B2
公开(公告)日:2018-11-20
申请号:US15652001
申请日:2017-07-17
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
IPC分类号: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L27/12 , H01L21/20 , H01L21/02
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
-
公开(公告)号:US10854724B2
公开(公告)日:2020-12-01
申请号:US16195591
申请日:2018-11-19
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
IPC分类号: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L21/02 , H01L29/78 , H01L27/12 , H01L21/20
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
-
9.
公开(公告)号:US11538938B2
公开(公告)日:2022-12-27
申请号:US16725501
申请日:2019-12-23
发明人: Che-Wei Yang , Hao-Hsiung Lin , Samuel C. Pan
IPC分类号: H01L29/78 , H01L29/10 , H01L29/267 , H01L29/66 , H01L21/02 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/36
摘要: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.
-
公开(公告)号:US11152251B2
公开(公告)日:2021-10-19
申请号:US15965076
申请日:2018-04-27
发明人: Che-Wei Yang , Hao-Hsiung Lin
IPC分类号: H01L21/76 , H01L21/768 , H01L21/48 , H01L21/56 , H01L21/324 , H01L21/762 , H01L29/66 , H01L21/263 , H01L21/311 , H01L23/31 , H01L21/8238 , H01L23/485
摘要: A method for manufacturing a semiconductor device includes forming a source region, a drain region, and a gate dielectric layer and a gate electrode covering a channel region between the source region and the drain region, forming an insulating layer over the source region, the drain region, and the gate electrode, forming first to third vias penetrating the insulating layer and exposing portions of the source region, the drain region, and the gate electrode, respectively, forming a source contact in the first via to electrically connect to the source region, forming a drain contact in the second via to electrically connect to the drain region, and forming a gate contact in the third via to electrically connect to the gate electrode. One or more of the first to third vias is formed by ion bombarding by a focused ion beam and followed by a thermal annealing process.
-
-
-
-
-
-
-
-
-