公开(公告)号：US20250167159A1

公开(公告)日：2025-05-22

申请号：US19033628

申请日：2025-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  G02B6/42 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

Abstract: A package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer and the package component. The second underfill is partially disposed in the trench.

公开(公告)号：US20250166895A1

公开(公告)日：2025-05-22

申请号：US19027577

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Hung-Yi Kuo ,  Nien-Fang Wu

IPC: H01F41/04 ,  H01F17/00 ,  H01L23/522 ,  H01L23/525

Abstract: A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

公开(公告)号：US20250159812A1

公开(公告)日：2025-05-15

申请号：US19028110

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jui-Pin Hung ,  Kuo-Chung Yee

IPC: H05K1/18 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34

Abstract: An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.

公开(公告)号：US20250096163A1

公开(公告)日：2025-03-20

申请号：US18964949

申请日：2024-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Tin-Hao Kuo ,  Hao-Yi Tsai

IPC: H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

公开(公告)号：US12255174B2

公开(公告)日：2025-03-18

申请号：US17809934

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo Lung Pan ,  Shu-Rong Chun ,  Chi-Hui Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065

Abstract: A package includes a package substrate, an interposer over and bonded to the package substrate, a first wafer over and bonding to the interposer, and a second wafer over and bonding to the first wafer. The first wafer has independent passive device dies therein. The second wafer has active device dies therein.

公开(公告)号：US12230513B2

公开(公告)日：2025-02-18

申请号：US18410365

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tin-Hao Kuo

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/18

Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

公开(公告)号：US12218026B2

公开(公告)日：2025-02-04

申请号：US18332957

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/367 ,  H01L21/683 ,  H01L23/373 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

公开(公告)号：US20240395791A1

公开(公告)日：2024-11-28

申请号：US18789288

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/538 ,  H01L25/07

Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

公开(公告)号：US20240387392A1

公开(公告)日：2024-11-21

申请号：US18786873

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hui-Jung Tsai ,  Hung-Jui Kuo ,  Chung-Shi Liu ,  Han-Ping Pu ,  Ting-Chu Ko

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

公开(公告)号：US20240387263A1

公开(公告)日：2024-11-21

申请号：US18789808

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chi-Hsi Wu ,  Wen-Chih Chiou ,  Tsang-Jiuh Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  An-Jhih Su

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L29/40

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.