公开(公告)号：US11532627B2

公开(公告)日：2022-12-20

申请号：US17093230

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Wei Ju Lee ,  Hou-Yu Chen ,  Chun-Fu Cheng

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/538

Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

公开(公告)号：US20220359731A1

公开(公告)日：2022-11-10

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US10276717B2

公开(公告)日：2019-04-30

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

公开(公告)号：US20150162445A1

公开(公告)日：2015-06-11

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US12009408B2

公开(公告)日：2024-06-11

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/0653 ,  H01L29/6656

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US11489063B2

公开(公告)日：2022-11-01

申请号：US16931930

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer.

公开(公告)号：US20210366907A1

公开(公告)日：2021-11-25

申请号：US17093230

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Wei Ju Lee ,  Hou-Yu Chen ,  Chun-Fu Cheng

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/538

Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.

公开(公告)号：US20210305249A1

公开(公告)日：2021-09-30

申请号：US17347218

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yu-Xuan Huang ,  Kuan-Lun Cheng ,  Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

公开(公告)号：US20210134718A1

公开(公告)日：2021-05-06

申请号：US16832833

申请日：2020-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Wei Ju Lee ,  Cheng-Ting Chung ,  Hou-Yu Chen ,  Chun-Fu Cheng ,  Kuan-Lun Cheng

IPC: H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US09455346B2

公开(公告)日：2016-09-27

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。