公开(公告)号：US10083860B2

公开(公告)日：2018-09-25

申请号：US15495901

申请日：2017-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang Liao ,  Chia-Yao Liang ,  Jui-Long Chen ,  Sheng-Yuan Lin ,  Yi-Lii Huang ,  Kuo-Hsi Lee ,  Po-An Chen

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.

公开(公告)号：US09165843B2

公开(公告)日：2015-10-20

申请号：US14598353

申请日：2015-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

IPC: G06F17/50 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/10 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

公开(公告)号：US09633860B2

公开(公告)日：2017-04-25

申请号：US14795751

申请日：2015-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang Liao ,  Chia-Yao Liang ,  Jui-Long Chen ,  Sheng-Yuan Lin ,  Yi-Lii Huang ,  Kuo-Hsi Lee ,  Po-An Chen

IPC: H01L29/06 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

公开(公告)号：US09158867B2

公开(公告)日：2015-10-13

申请号：US13647643

申请日：2012-10-09

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Chun-Hsien Lin ,  Jui-Long Chen ,  Hui-Yun Chao ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G06F19/00 ,  G06F17/50 ,  G03F7/20

CPC classification number: G06F17/50 ,  G03F7/70533 ,  G03F7/70616 ,  G05B23/024

Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。

公开(公告)号：US08938698B2

公开(公告)日：2015-01-20

申请号：US14108392

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

IPC: G06F17/50

CPC classification number: H01L22/20 ,  H01L22/10 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract translation: 提供了一种自动检测半导体晶片工艺的故障模式的系统和方法。 该方法包括接收从测试多个半导体晶片收集的测试数据集，为每个晶片形成相应的晶片图，确定每个相应的晶片图是否包括一个或多个相应的对象，选择被确定为包括的晶片图 一个或多个相应的对象，选择一个或多个对象索引，用于在每个相应的选定的晶片图中选择相应的对象，确定每个相应选择的晶片图中的多个对象索引值，在每个相应的选定晶片图中选择一个对象， 各个所选晶片中的每一个的相应特征，对各个所选晶片图中的每一个分类各自的图案，并使用相应的晶片指纹来调整半导体制造工艺的一个或多个参数。

公开(公告)号：US20140100684A1

公开(公告)日：2014-04-10

申请号：US13647643

申请日：2012-10-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Chun-Hsien Lin ,  Jui-Long Chen ,  Hui-Yun Chao ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G06F19/00

CPC classification number: G06F17/50 ,  G03F7/70533 ,  G03F7/70616 ,  G05B23/024

Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。