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    Scanner overlay correction system and method
    1.
    发明授权
    Scanner overlay correction system and method 有权
    扫描仪覆盖校正系统和方法

    公开(公告)号：US09442392B2

    公开(公告)日：2016-09-13

    申请号：US14585457

    申请日：2014-12-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yen-Di Tsen ,  Yi-Ping Hsieh ,  Chen-Yen Huang ,  Shin-Rung Lu ,  Jong-I Mou

    IPC: G03F7/20 ,  G03F9/00 ,  H01L21/00 ,  H01L21/027 ,  H01L21/66

    CPC classification number: G03F7/70633 ,  G03F9/7003 ,  G03F9/7019 ,  H01L21/0274 ,  H01L22/12 ,  H01L22/20

    Abstract: A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

    Abstract translation: 提供了一种处理第一和第二半导体晶片的方法。 第一和第二半导体晶片中的每一个在第一层上具有第一层和第二层。 使用第一场间校正和第一场内校正在第一半导体晶片上的第一层上执行第一光刻处理。 确定第一光刻工艺的覆盖误差。 基于第一场间校正，第一场校正和测量的重叠误差来计算第二场校正和第二场校正。 基于第二场间校正和第二场内校正，在第二半导体晶片上的第二层上执行第二光刻处理。

    Scanner overlay correction system and method
    2.
    发明授权
    Scanner overlay correction system and method 有权
    扫描仪覆盖校正系统和方法

    公开(公告)号：US09082661B2

    公开(公告)日：2015-07-14

    申请号：US14514467

    申请日：2014-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Di Tsen ,  Shin-Rung Lu ,  Jong-I Mou

    IPC: H01L21/00 ,  H01L21/66 ,  H01L21/67

    CPC classification number: H01L22/12 ,  G03F9/7003 ,  G03F9/7019 ,  H01L21/67063 ,  H01L21/67092

    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

    Abstract translation: 一种方法包括在多个基板上执行半导体制造工艺。 多个基板被分成第一子集和第二子集。 在多个基板的第二子集上执行返工处理，但不在第一子集上。 针对多个基板的第一和第二子集中的每个相应的一个计算出用于光刻工艺的至少一个曝光参数的相应平均值。 应用扫描器覆盖校正和平均校正以暴露已经执行返工处理的第二多个基板。 平均校正基于计算的平均值。

    Overlay Abnormality Gating by Z Data
    3.
    发明申请
    Overlay Abnormality Gating by Z Data 有权
    叠加异常门控Z数据

    公开(公告)号：US20150015870A1

    公开(公告)日：2015-01-15

    申请号：US13940335

    申请日：2013-07-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Hsien Lin ,  Kuo-Hung Chao ,  Yi-Ping Hsieh ,  Yen-Di Tsen ,  Jui-Chun Peng ,  Heng-Hsin Liu ,  Jong-I Mou

    IPC: H01L21/66 ,  G01B21/02 ,  G01B21/20 ,  G01N21/95

    CPC classification number: H01L22/12 ,  G01B11/24 ,  G01B13/065 ,  G01B2210/56 ,  G01N21/9501 ,  G03F7/00 ,  G03F7/70533 ,  G03F9/7003 ,  H01L22/20 ,  H01L22/30

    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

    Abstract translation: 本公开涉及一种监测晶片形貌的方法。 测量设置在晶片表面上的多个第一对准形状的位置和取向。 作为晶片位置的函数的晶片形貌通过使晶片经受对准，同时最小化晶片和图案形成装置之间的未对准并使辐射在表面上的焦点最大化来建模。 不可校正误差被确定为模拟晶片形貌与测量的晶片形貌之间的差异。 对于晶片确定每场的最大不可校正误差，并且在层内和跨层中确定在批次的每个晶片内的每个场上的每个场的最大不可校正误差的平均变化。 然后根据一组统计过程控制规则验证这些值，以确定它们是否在制造过程的规格限制内。

    Scanner overlay correction system and method
    4.
    发明授权
    Scanner overlay correction system and method 有权
    扫描仪覆盖校正系统和方法

    公开(公告)号：US08889434B2

    公开(公告)日：2014-11-18

    申请号：US13716340

    申请日：2012-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Di Tsen ,  Shin-Rung Lu ,  Jong-I Mou

    IPC: H01L21/00 ,  H01L21/66

    CPC classification number: H01L22/12 ,  G03F9/7003 ,  G03F9/7019 ,  H01L21/67063 ,  H01L21/67092

    Abstract: A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

    Abstract translation: 一种方法包括在多个基板上执行半导体制造工艺。 多个基板被分成第一子集和第二子集。 在多个基板的第二子集上执行返工处理，但不在第一子集上。 对于多个基板的第一和第二子集中的每个相应的一个，计算光刻工艺的至少一个曝光参数的相应平均值。 应用扫描器覆盖校正和平均校正以暴露已经执行返工处理的第二多个基板。 平均校正基于计算的平均值。

    Overlay abnormality gating by Z data
    7.
    发明授权
    Overlay abnormality gating by Z data 有权
    叠加异常门控Z数据

    公开(公告)号：US09123583B2

    公开(公告)日：2015-09-01

    申请号：US13940335

    申请日：2013-07-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Hsien Lin ,  Kuo-Hung Chao ,  Yi-Ping Hsieh ,  Yen-Di Tsen ,  Jui-Chun Peng ,  Heng-Hsin Liu ,  Jong-I Mou

    IPC: G01N21/00 ,  H01L21/66 ,  G01N21/95 ,  G03F7/00 ,  G01B13/06 ,  G01B11/24

    CPC classification number: H01L22/12 ,  G01B11/24 ,  G01B13/065 ,  G01B2210/56 ,  G01N21/9501 ,  G03F7/00 ,  G03F7/70533 ,  G03F9/7003 ,  H01L22/20 ,  H01L22/30

    Abstract: The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.

    Abstract translation: 本公开涉及一种监测晶片形貌的方法。 测量设置在晶片表面上的多个第一对准形状的位置和取向。 作为晶片位置的函数的晶片形貌通过使晶片经受对准，同时最小化晶片和图案形成装置之间的未对准并使辐射在表面上的焦点最大化来建模。 不可校正误差被确定为模拟晶片形貌与测量的晶片形貌之间的差异。 对于晶片确定每场的最大不可校正误差，并且在层内和跨层中确定在批次的每个晶片内的每个场上的每个场的最大不可校正误差的平均变化。 然后根据一组统计过程控制规则验证这些值，以确定它们是否在制造过程的规格限制内。

    2D/3D analysis for abnormal tools and stages diagnosis
    8.
    发明授权
    2D/3D analysis for abnormal tools and stages diagnosis 有权
    2D / 3D分析用于异常工具和阶段诊断

    公开(公告)号：US09158867B2

    公开(公告)日：2015-10-13

    申请号：US13647643

    申请日：2012-10-09

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Chun-Hsien Lin ,  Jui-Long Chen ,  Hui-Yun Chao ,  Jong-I Mou ,  Chin-Hsiang Lin

    IPC: G06F19/00 ,  G06F17/50 ,  G03F7/20

    CPC classification number: G06F17/50 ,  G03F7/70533 ,  G03F7/70616 ,  G05B23/024

    Abstract: A method for analyzing abnormalities in a semiconductor processing system provides performing an analysis of variance on a production history associated with each of a plurality of tools at each of a plurality of process steps for each of a plurality of processed wafers, and key process steps are identified. A regression analysis on a plurality of measurements of the plurality of wafers at each process step is performed and key measurement parameters are identified. An analysis of covariance on the key measurement parameters and key process steps, and the key process steps are ranked based on an f-ratio, therein ranking an abnormality of the key process steps. Further, the plurality of tools associated with each of the key process steps are ranked based on an orthogonal t-ratio associated with an analysis of covariance, therein ranking an abnormality each tool associated with the key process steps.

    Abstract translation: 一种用于分析半导体处理系统中的异常的方法，提供了在多个处理晶片中的每一个的多个处理步骤中的每一个处执行与多个工具中的每一个相关联的生产历史上的方差分析，并且关键处理步骤 确定。 执行在每个处理步骤对多个晶片的多个测量的回归分析，并且识别关键测量参数。 关键测量参数和关键过程步骤的协方差分析以及关键过程步骤基于f比进行排序，其中排列关键过程步骤的异常。 此外，与关键处理步骤中的每一个相关联的多个工具基于与协方差分析相关联的正交t比进行排序，其中对与关键处理步骤相关联的每个工具进行排序。

    Multi-zone temperature control for semiconductor wafer
    9.
    发明授权
    Multi-zone temperature control for semiconductor wafer 有权
    半导体晶圆的多区域温度控制

    公开(公告)号：US09023664B2

    公开(公告)日：2015-05-05

    申请号：US13777212

    申请日：2013-02-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

    IPC: H01L21/00 ,  H01L21/66 ,  H01L21/67

    CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

    Abstract translation: 提供了一种用于控制电路的关键尺寸（CD）的装置和方法。 一种装置包括控制器，用于在第一基板上的蚀刻膜中的电路图案的各个位置处接收CD测量值，以及用于在第二基板上形成膜材料的第二膜的单晶片室。 单个晶片室响应于来自控制器的信号，以基于测量的CD来局部地调整第二胶片的厚度。 一种方法提供了蚀刻第一衬底上的膜的电路图案，测量电路图案的CD，基于所测量的CD调整单晶片室以在第二半导体衬底上形成第二膜。 基于测量的CD来局部地调整第二膜厚度。

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