公开(公告)号：US11966241B2

公开(公告)日：2024-04-23

申请号：US17650668

申请日：2022-02-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huan-Neng Chen ,  Yen-Lin Liu ,  Chia-Wei Hsu ,  Jo-Yu Wu ,  Chang-Fen Hu ,  Shao-Yu Li ,  Bo-Ting Chen

IPC分类号： G05F1/595 ,  G05F1/575 ,  H03K19/0175

CPC分类号： G05F1/595 ,  G05F1/575 ,  H03K19/017509

摘要： A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

公开(公告)号：US11967958B2

公开(公告)日：2024-04-23

申请号：US17538154

申请日：2021-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huan-Neng Chen ,  Chang-Fen Hu ,  Shao-Yu Li

IPC分类号： H03K5/01 ,  H03K19/20 ,  H03K5/00

CPC分类号： H03K5/01 ,  H03K19/20 ,  H03K2005/00013

摘要： In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

公开(公告)号：US11646313B2

公开(公告)日：2023-05-09

申请号：US17357803

申请日：2021-06-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chang-Fen Hu ,  Shao-Yu Li ,  Kuo-Ji Chen ,  Chih-Peng Lin ,  Chuei-Tang Wang ,  Ching-Fang Chen

IPC分类号： H01L27/092 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L27/092 ,  H01L23/5383 ,  H01L25/0655 ,  H01L25/50 ,  H01L25/0657

摘要： A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

公开(公告)号：US20220352880A1

公开(公告)日：2022-11-03

申请号：US17538154

申请日：2021-11-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huan-Neng Chen ,  Chang-Fen Hu ,  Shao-Yu Li

IPC分类号： H03K5/01 ,  H03K19/20

摘要： In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

公开(公告)号：US09117678B2

公开(公告)日：2015-08-25

申请号：US14106518

申请日：2013-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chang-Fen Hu ,  Wun-Jie Lin

IPC分类号： H01L29/92 ,  H01L27/02

CPC分类号： H01L27/0288 ,  H01L27/0255 ,  H01L28/20

摘要： A semiconductor device includes a semiconductor region, a first active region in the semiconductor region, a second active region in the semiconductor region, and a conductive gate disposed above the first active region and the second active region. A first contact of the conductive gate is configured to couple to a first node of a circuit associated with the semiconductor device. Moreover, a second contact of the conductive gate is configured to couple to a second node of a circuit associated with the semiconductor device. A resistive device is defined between the first contact and the second contact.

摘要翻译： 半导体器件包括半导体区域，半导体区域中的第一有源区，半导体区域中的第二有源区，以及设置在第一有源区和第二有源区上方的导电栅。 导电栅极的第一接触被配置为耦合到与半导体器件相关联的电路的第一节点。 此外，导电栅极的第二接触被配置为耦合到与半导体器件相关联的电路的第二节点。 电阻器件被限定在第一触点和第二触点之间。