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公开(公告)号：US20230034125A1
公开(公告)日：2023-02-02
申请号：US17444068
申请日：2021-07-30
发明人： I-Wen WU , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L29/417 , H01L29/66 , H01L21/8234 , H01L29/40
摘要： Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.
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公开(公告)号：US20210005602A1
公开(公告)日：2021-01-07
申请号：US17024006
申请日：2020-09-17
发明人： Chun-Han CHEN , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG , Jr-Hung LI , Bo-Cyuan LU
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/423 , H01L29/66
摘要： A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a conductive layer formed over the first gate structure. The FinFET device structure includes a first capping layer formed over the conductive layer, and a top surface of the conductive layer is in direct contact with a bottom surface of the first capping layer.
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公开(公告)号：US20220359683A1
公开(公告)日：2022-11-10
申请号：US17313368
申请日：2021-05-06
发明人： Kai-Hsuan LEE , I-Wen WU , Chen-Ming LEE , Jian-Hao CHEN , Fu-Kai YANG , Feng-Cheng YANG , Mei-Yun WANG , Yen-Ming CHEN
IPC分类号： H01L29/417 , H01L29/78 , H01L29/66 , H01L29/40
摘要： A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.
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公开(公告)号：US20230317805A1
公开(公告)日：2023-10-05
申请号：US17700357
申请日：2022-03-21
发明人： Shih-Che LIN , Tzu-Yang HO , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L21/768 , H01L29/66 , H01L29/78 , H01L29/417
CPC分类号： H01L29/41791 , H01L21/76843 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a gate electrode layer disposed over a substrate, a source/drain epitaxial feature disposed over the substrate, a first hard mask layer disposed over the gate electrode layer, and a contact etch stop layer (CESL) disposed over the source/drain epitaxial feature. The structure further includes a first interlayer dielectric (ILD) layer disposed on the CESL and a first treated portion of a second hard mask layer disposed on the CESL and the first ILD layer. A top surface of the first hard mask layer and a top surface of the first treated portion of the second mask layer are substantially coplanar. The structure further includes an etch stop layer disposed on the first hard mask layer and the first treated portion of the second mask layer.
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公开(公告)号：US20230268411A1
公开(公告)日：2023-08-24
申请号：US17678288
申请日：2022-02-23
发明人： Kai-Hsuan LEE , Shih-Che LIN , Po-Yu HUANG , Shih-Chieh WU , I-Wen WU , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L29/423 , H01L29/06 , H01L29/786 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/42392 , H01L29/0665 , H01L29/78618 , H01L29/78696 , H01L29/66742 , H01L29/66545 , H01L21/823412 , H01L21/823418 , H01L21/823468
摘要： A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.
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6.发明申请公开(公告)号：US20220328622A1
公开(公告)日：2022-10-13
申请号：US17225324
申请日：2021-04-08
发明人： Chung-Hao CAI , Chun-Po CHANG , Chien-Yuan CHEN , Yen-Jun HUANG , Ting FANG , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L29/06 , H01L29/66 , H01L21/8234
摘要： A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.
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公开(公告)号：US20240355708A1
公开(公告)日：2024-10-24
申请号：US18304913
申请日：2023-04-21
发明人： Po-Yu HUANG , Shih-Chieh WU , Chen-Ming LEE , I-Wen WU , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L23/48 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696
摘要： One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.
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8.发明申请公开(公告)号：US20220328639A1
公开(公告)日：2022-10-13
申请号：US17854388
申请日：2022-06-30
发明人： Ting FANG , Da-Wen LIN , Fu-Kai YANG , Chen-Ming LEE , Mei-Yun WANG
IPC分类号： H01L29/423 , H01L29/78 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/45
摘要： A method for forming a FinFET device structure and method for forming the same is provided. The method includes forming an isolation structure over a substrate and forming a first dielectric layer over the isolation structure. The method includes forming a gate structure in the first dielectric layer and forming a deep trench through the first dielectric layer and the isolation structure. The method also includes forming an S/D trench in the first dielectric layer and filling a metal material in the deep trench and the S/D trench to form a deep contact structure and the S/D contact structure. A bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.
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公开(公告)号：US20240154015A1
公开(公告)日：2024-05-09
申请号：US18187847
申请日：2023-03-22
发明人： Jui-Lin CHEN , Hsin-Wen SU , Chih-Ching WANG , Chen-Ming LEE , Chung-I YANG , Yi-Feng TING , Jon-Hsu HO , Lien-Jung HUNG , Ping-Wei WANG
IPC分类号： H01L29/423 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/786 , H10B10/00
CPC分类号： H01L29/42392 , H01L21/76877 , H01L21/823821 , H01L23/5226 , H01L27/0886 , H01L29/0673 , H01L29/66439 , H01L29/66454 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , H10B10/12
摘要： A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
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公开(公告)号：US20240096985A1
公开(公告)日：2024-03-21
申请号：US18519714
申请日：2023-11-27
发明人： I-Wen WU , Chen-Ming LEE , Fu-Kai YANG , Mei-Yun WANG
IPC分类号： H01L29/417 , H01L21/8234 , H01L29/40 , H01L29/66
CPC分类号： H01L29/41775 , H01L21/823431 , H01L29/401 , H01L29/66545 , H01L29/6681
摘要： Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.
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