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公开(公告)号:US11756842B2
公开(公告)日:2023-09-12
申请号:US17448002
申请日:2021-09-17
发明人: Chun-Liang Lu , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee
CPC分类号: H01L22/34 , H01L23/585 , H01L24/08 , H01L24/80 , H01L2224/08135 , H01L2224/80895
摘要: A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.
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公开(公告)号:US11569289B2
公开(公告)日:2023-01-31
申请号:US17410666
申请日:2021-08-24
发明人: Yun-Wei Cheng , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee , Ying-Hao Chen
IPC分类号: H01L27/146 , H01L23/00
摘要: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.
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公开(公告)号:US11569288B2
公开(公告)日:2023-01-31
申请号:US17225701
申请日:2021-04-08
发明人: Yun-Wei Cheng , Chun-Wei Chia , Chun-Hao Chou , Kuo-Cheng Lee , Ying-Hao Chen
IPC分类号: H01L27/146 , H01L23/00
摘要: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.
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公开(公告)号:US10985199B2
公开(公告)日:2021-04-20
申请号:US16591891
申请日:2019-10-03
发明人: Yun-Wei Cheng , Chun-Hao Chou , Kuo-Cheng Lee , Ying-Hao Chen , Chun-Wei Chia
IPC分类号: H01L27/146 , H01L23/00
摘要: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.
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