公开(公告)号：US20240387595A1

公开(公告)日：2024-11-21

申请号：US18789982

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Chien HSIEH ,  Kuo-Cheng Lee ,  Ying-Hao Chen ,  Yun-Wei Cheng

IPC: H01L27/146

Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.

公开(公告)号：US20150333007A1

公开(公告)日：2015-11-19

申请号：US14809580

申请日：2015-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Chih Chen ,  Ying-Hao Chen ,  Chi-Cherng Jeng ,  Volume Chien ,  Fu-Tsun Tsai ,  Kun-Huei Lin

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/31

CPC classification number: H01L23/5226 ,  G06F17/5077 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16145 ,  H01L2224/29006 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

Abstract translation: 半导体器件包括包括多个第一层金属焊盘的第一层，形成在第一层顶部上的第二层，第二层包括多个第二层金属焊盘，以及将第一层金属焊盘连接到第二层金属焊盘的通孔 层金属垫。 第一层金属焊盘和第二层金属焊盘之间的表面积重叠低于规定的阈值。

公开(公告)号：US20150001658A1

公开(公告)日：2015-01-01

申请号：US13929172

申请日：2013-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shang-Yen Wu ,  I-Chih Chen ,  Yi-Sheng Liu ,  Volume Chien ,  Fu-Tsun Tsai ,  Chi-Cherng Jeng ,  Ying-Hao Chen

IPC: H01L31/02

CPC classification number: H01L27/1464 ,  H01L24/05 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.

Abstract translation: 提供了一种包括设置在基板上的光感测区域的半导体器件，其包括在衬垫元件下方具有一个或多个图案化层的接合结构。 焊盘元件可以耦合到光感测区域，并且可以形成在设置在衬底上的第一金属层中。 器件的第二金属层具有第一结合区域，第二金属层的位于衬垫元件下面的区域。 第二金属层的该第一接合区域包括插入介电体的多个导电线图案。 通孔连接垫元件和第二金属层。

公开(公告)号：US11569288B2

公开(公告)日：2023-01-31

申请号：US17225701

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Wei Cheng ,  Chun-Wei Chia ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Ying-Hao Chen

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.

公开(公告)号：US20210273009A1

公开(公告)日：2021-09-02

申请号：US17322769

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Volume Chien ,  I-Chih Chen ,  Hsin-Chi Chen ,  Hung-Ta Huang ,  Ying-Hao Chen ,  Ying-Lang Wang

IPC: H01L27/146 ,  H01L23/00 ,  H01L21/764

Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.

公开(公告)号：US10985199B2

公开(公告)日：2021-04-20

申请号：US16591891

申请日：2019-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yun-Wei Cheng ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Ying-Hao Chen ,  Chun-Wei Chia

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.

公开(公告)号：US20160148967A1

公开(公告)日：2016-05-26

申请号：US15012300

申请日：2016-02-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Volume Chien ,  I-Chih Chen ,  Hsin-Chi Chen ,  Hung-Ta Huang ,  Ying-Hao Chen ,  Ying-Lang Wang

IPC: H01L27/146 ,  H01L21/764 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L21/764 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/14 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2224/05075 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08054 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15788 ,  H04N5/335 ,  H01L2924/00

Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.

Abstract translation: 焊盘结构包括互连层，互连层上的隔离层，导电焊盘和一个或多个非导电应力释放结构。 导电焊盘包括隔离层上的平面部分，以及至少延伸穿过隔离层和互连层的一个或多个桥接部分，用于建立与其的电接触，其中在一个或多个桥接部分中存在沟槽。 一个或多个非导电应力释放结构设置在隔离层和导电垫之间。 从顶视图，沟槽被一个或多个非导电应力释放结构中的一个围绕。

公开(公告)号：US12224297B2

公开(公告)日：2025-02-11

申请号：US18156693

申请日：2023-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Wei Cheng ,  Chun-Wei Chia ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Ying-Hao Chen

IPC: H01L27/146 ,  H01L23/00

Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.

公开(公告)号：US11569289B2

公开(公告)日：2023-01-31

申请号：US17410666

申请日：2021-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Wei Cheng ,  Chun-Wei Chia ,  Chun-Hao Chou ,  Kuo-Cheng Lee ,  Ying-Hao Chen

IPC: H01L27/146 ,  H01L23/00

Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

公开(公告)号：US09659859B2

公开(公告)日：2017-05-23

申请号：US14809580

申请日：2015-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Chih Chen ,  Ying-Hao Chen ,  Chi-Cherng Jeng ,  Volume Chien ,  Fu-Tsun Tsai ,  Kun-Huei Lin

IPC: H01L23/522 ,  H01L23/48 ,  G06F17/50 ,  H01L23/31 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/5226 ,  G06F17/5077 ,  H01L21/76805 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/16145 ,  H01L2224/29006 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00012

Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.