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    IMAGE SENSOR WITH OVERLAP OF BACKSIDE TRENCH ISOLATION STRUCTURE AND VERTICAL TRANSFER GATE
    4.
    发明申请
    IMAGE SENSOR WITH OVERLAP OF BACKSIDE TRENCH ISOLATION STRUCTURE AND VERTICAL TRANSFER GATE 有权

    公开(公告)号：US20220367537A1

    公开(公告)日：2022-11-17

    申请号：US17867760

    申请日：2022-07-19

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wei Chuang Wu ,  Yen-Yu Chen ,  Chih-Kuan Yu

    IPC分类号： H01L27/146

    摘要： Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

    Interconnect Structure for Stacked Device
    7.
    发明申请
    Interconnect Structure for Stacked Device 有权

    公开(公告)号：US20210233813A1

    公开(公告)日：2021-07-29

    申请号：US17227703

    申请日：2021-04-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shu-Ting Tsai ,  Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Sheng-Chau Chen ,  Shih Pei Chou ,  Chia-Chieh Lin

    IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

    摘要： A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

    Interconnect structure for stacked device and method
    9.
    发明授权
    Interconnect structure for stacked device and method 有权

    公开(公告)号：US10535706B2

    公开(公告)日：2020-01-14

    申请号：US16220441

    申请日：2018-12-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chun-Chieh Chuang ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Feng-Chi Hung ,  Tzu-Hsuan Hsu ,  Shu-Ting Tsai ,  Min-Feng Kao

    IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L21/768 ,  H01L23/48

    摘要： A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.