公开(公告)号：US12131992B2

公开(公告)日：2024-10-29

申请号：US18489864

申请日：2023-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Chang ,  Hsuan-Ming Huang ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Mingni Chang ,  Ming-Yih Wang

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L22/14 ,  H01L23/53209

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

公开(公告)号：US12099792B2

公开(公告)日：2024-09-24

申请号：US18341400

申请日：2023-06-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsien Yu Tseng ,  Amit Kundu ,  Chun-Wei Chang ,  Szu-Lin Liu ,  Sheng-Feng Liu

IPC: G06F30/398 ,  G06F111/20 ,  G06F119/08 ,  G06F119/10 ,  H01L29/78

CPC classification number: G06F30/398 ,  G06F2111/20 ,  G06F2119/08 ,  G06F2119/10 ,  H01L29/785

Abstract: An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

公开(公告)号：US12040336B2

公开(公告)日：2024-07-16

申请号：US18078455

申请日：2022-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Feng-Jia Shiu ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Chun-Wei Chang ,  Wei-Cheng Hsu ,  Wei Chuang Wu ,  Yimin Huang

IPC: H01L27/146

CPC classification number: H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14641 ,  H01L27/14689

Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

公开(公告)号：US11830806B2

公开(公告)日：2023-11-28

申请号：US17244783

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Chang ,  Hsuan-Ming Huang ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Mingni Chang ,  Ming-Yih Wang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L22/14 ,  H01L23/53209

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

公开(公告)号：US11658031B2

公开(公告)日：2023-05-23

申请号：US17303522

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wei-Chao Chiu ,  Yong-Jin Liou ,  Yu-Wen Chen ,  Chun-Wei Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu

IPC: H01L21/04 ,  H01L27/146 ,  H01L21/033 ,  H01L21/266

CPC classification number: H01L21/0332 ,  H01L21/0465 ,  H01L21/266

Abstract: Implantation mask formation techniques described herein include increasing an initial aspect ratio of a pattern in an implantation mask by non-lithography techniques, which may include forming a resist hardening layer on the implantation mask. The pattern may be formed by photolithography techniques to the initial aspect ratio that reduces or minimizes the likelihood of pattern collapse during formation of the pattern. Then, the resist hardening layer is formed on the implantation mask to increase the height of the pattern and reduce the width of the pattern, which increases the aspect ratio between the height of the openings or trenches and the width of the openings or trenches of the pattern. In this way, the pattern in the implantation mask may be formed to an ultra-high aspect ratio in a manner that reduces or minimizes the likelihood of pattern collapse during formation of the pattern.

公开(公告)号：US09651869B2

公开(公告)日：2017-05-16

申请号：US14680546

申请日：2015-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun-Wei Chang ,  Wang-Pen Mo ,  Hung-Chang Hsieh

IPC: G03F7/20 ,  H01L21/308 ,  H01L21/027 ,  G03F7/00 ,  H01L21/3105 ,  H01L21/311

CPC classification number: G03F7/20 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/3085 ,  H01L21/31058 ,  H01L21/31144

Abstract: A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.

公开(公告)号：US09627326B2

公开(公告)日：2017-04-18

申请号：US15165834

申请日：2016-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Chun-Wei Chang ,  Kai-Chun Hsu ,  Chih-Yu Lai ,  Wei-Cheng Hsu ,  Hsiao-Hui Tseng ,  Shih Pei Chou ,  Shyh-Fann Ting ,  Tzu-Hsuan Hsu ,  Ching-Chun Wang ,  Yeur-Luen Tu ,  Dun-Nian Yaung

IPC: H01L21/762 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/7621 ,  H01L21/76224 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/0649 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

公开(公告)号：US20150255400A1

公开(公告)日：2015-09-10

申请号：US14203242

申请日：2014-03-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Chun-Wei Chang ,  Kai-Chun Hsu ,  Chih-Yu Lai ,  Wei-Cheng Hsu ,  Hsiao-Hui Tseng ,  Shih Pei Chou ,  Shyh-Fann Ting ,  Tzu-Hsuan Hsu ,  Ching-Chun Wang ,  Yeur-Luen Tu ,  Dun-Nian Yaung

IPC: H01L23/544 ,  H01L21/762

CPC classification number: H01L23/544 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/7621 ,  H01L21/76224 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/0649 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks.

Abstract translation: 介绍了一种制造非STI CMOS图像传感器对准标记的方法。 在一些实施例中，可以在晶片上同时形成零层对准标记和活性物质对准标记。 可以将晶片的衬底图案化以在衬底中形成一个或多个凹槽。 可以使用例如场氧化方法和/或合适的沉积方法用电介质材料填充凹部。 通过上述过程形成的结构可以对应于零层对准标记的元素和/或对应于有源区对准标记的元件。

公开(公告)号：US20230109829A1

公开(公告)日：2023-04-13

申请号：US18078455

申请日：2022-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Seiji Takahashi ,  Chen-Jong Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Feng-Jia Shiu ,  Jen-Cheng Liu ,  Jhy-Jyi Sze ,  Chun-Wei Chang ,  Wei-Cheng Hsu ,  Wei Chuang Wu ,  Yimin Huang

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

公开(公告)号：US11288437B2

公开(公告)日：2022-03-29

申请号：US17121312

申请日：2020-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsien Yu Tseng ,  Chun-Wei Chang ,  Szu-Lin Liu ,  Amit Kundu ,  Sheng-Feng Liu

IPC: G06F30/398 ,  H01L29/78 ,  G06F111/20 ,  G06F119/08 ,  G06F119/10

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.