公开(公告)号：US20250063764A1

公开(公告)日：2025-02-20

申请号：US18449824

申请日：2023-08-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun LIN ,  Ming-Heng TSAI

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming a first gate stack and a second gate stack wrapped around the nanostructure stack. The method includes forming a first source/drain structure in the nanostructure stack and between the first gate stack and the second gate stack. The method includes removing the second gate stack, the nanostructure stack and the fin under the second gate stack to form a trench passing through the nanostructure stack and the fin. The method includes forming a dielectric isolation structure in the trench. The method includes removing the first gate stack and the first nanostructure. The method includes forming a third gate stack wrapped around the second nanostructure. The method includes forming a first contact structure over the first source/drain structure.

公开(公告)号：US20250006827A1

公开(公告)日：2025-01-02

申请号：US18342910

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun LIN ,  Jhon-Jhy LIAW

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an isolation structure formed over a substrate, and first nanostructures formed over an isolation structure along a first direction. The semiconductor includes second nanostructures adjacent to the first nanostructure along the first direction. The semiconductor also includes a dielectric wall between the first nanostructures and the second nanostructures, and the dielectric wall includes a low-k dielectric material. The dielectric wall is in direct contact with the first nanostructures and the second nanostructures, and a top surface of the dielectric wall is higher than a top surface of the isolation structure. The semiconductor includes a gate structure formed over the first nanostructures along a second direction, and a cutting structure formed over the dielectric wall. The gate structure is divided into two portions by the cutting structure.

公开(公告)号：US20250006811A1

公开(公告)日：2025-01-02

申请号：US18344860

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun LIN ,  Chun-Wing Yeung ,  Feng-Ming CHANG ,  Jhon Jhy Liaw

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, semiconductor nanosheets vertically stacked upon one another and disposed above the semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, inner spacers laterally covering the gate structure and interposed between the semiconductor nanosheets, and source/drain (S/D) regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions. A bottommost inner spacer of the inner spacers underlying a bottommost semiconductor nanosheet of the semiconductor nanosheets is thinner than a topmost inner spacer of the inner spacers underlying a topmost semiconductor nanosheet of the semiconductor nanosheets. The S/D regions are separated from the gate structure through the inner spacers.

公开(公告)号：US20240413231A1

公开(公告)日：2024-12-12

申请号：US18332507

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huang-Chao CHANG ,  Ta-Chun LIN ,  Chun-Sheng LIANG ,  Jhon-Jhy LIAW

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a vertical stack including nanostructures, and a gate structure wrapping around each of the nanostructures. The nanostructures are suspended and vertically arranged over the substrate. The gate structure includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The semiconductor structure further includes inner spacers and gate spacers. The inner spacers are formed on opposite sides of the gate structure, between the nanostructures, and separating the nanostructures from each other. The gate spacers are formed on the opposite sides of the gate structure and over a topmost one of the nanostructures. The gate dielectric layer includes a first portion formed on the nanostructures and a second portion extending from the first portion. The first portion and the second portion have a first thickness and a second thickness, respectively. The first thickness is greater than the second thickness.

公开(公告)号：US20240322024A1

公开(公告)日：2024-09-26

申请号：US18186211

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Han Tsai ,  Pin Chun Shen ,  Ta-Chun LIN ,  Chun-Sheng Liang

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes first semiconductor channel layers, second semiconductor channel layers, a dielectric wall, a gate structure, a source/drain electrode and an inner spacer. The first semiconductor channel layers are stacked vertically apart along a first direction over a substrate. The second semiconductor channel layers are stacked vertically apart along the first direction over the substrate. The dielectric wall is disposed between and separates the first semiconductor channel layers and the second first semiconductor channel layers, wherein the dielectric wall comprises a liner and a dielectric wall material disposed over the liner. The gate structure extends along a second direction perpendicular to the first direction disposed crossing over a channel region of the first fin structure and a channel region of the second fin structure. The source/drain electrode is in contact with the first semiconductor channel layers. The inner spacer is enclosed by the first semiconductor channel layers, the gate structure, the dielectric wall and the source/drain electrode, wherein the inner spacer is in contact with the dielectric wall material of the dielectric wall.

公开(公告)号：US20240250161A1

公开(公告)日：2024-07-25

申请号：US18099732

申请日：2023-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Heng TSAI ,  Chun-Sheng LIANG ,  Ta-Chun LIN

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545

Abstract: Embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a source/drain contact disposed above the source/drain feature, a gate spacer disposed between the gate electrode layer and the source/drain contact, and an isolation structure extending through the gate electrode layer. The isolation structure includes a first portion having three sides covered by the gate electrode layer, the first portion having a top surface at a first elevation, and a second portion extended outwardly from the first portion, the second portion having a top surface at a second elevation that is lower than the first elevation.

公开(公告)号：US20240203829A1

公开(公告)日：2024-06-20

申请号：US18173627

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ta-Chun LIN ,  Jhon-Jhy LIAW

IPC: H01L23/48 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/78696

Abstract: A semiconductor device includes a transistor structure disposed on a first side of a substrate and a back-side via structure disposed on a second side of the substrate opposite to the first side. The transistor structure includes a pair of epitaxial structures and a channel feature extending in a channel length direction to be disposed between the epitaxial structures. The channel feature has a width in a channel width direction transverse to the channel length direction. The back-side via structure extends through the substrate so as to be connected to a bottom surface and a sidewall surface of a lower portion of a corresponding one of the epitaxial structures. The back-side via structure has a width in the channel width direction, which is greater than the width of the channel feature.

公开(公告)号：US20240120337A1

公开(公告)日：2024-04-11

申请号：US18097263

申请日：2023-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ta-Chun LIN ,  Chih-Hung HSIEH ,  Chun-Sheng LIANG ,  Wen-Chiang HONG ,  Chun-Wing YEUNG ,  Kuo-Hua PAN ,  Chih-Hao CHANG ,  Jhon Jhy LIAW

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

公开(公告)号：US20240113121A1

公开(公告)日：2024-04-04

申请号：US18170259

申请日：2023-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Heng TSAI ,  Ta-Chun LIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/0928 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Semiconductor devices are provided. A semiconductor device includes a first well region having a first conductivity type, a second well region having a second conductivity type, a cell, and a pickup tap cell. The cell includes a first forksheet structure. The first forksheet structure includes a first transistor formed over the first well region, a second transistor formed over the second well region, and a first wall structure disposed on and extending along an interface between the first and second well regions. The first transistor and the second transistor are disposed on opposite sides of the first wall structure. The pickup tap cell includes a nanosheet structure. The nanosheet structure includes a pickup transistor formed over the second well region. Source/drain features of the first transistor and the pickup transistor have the second conductivity type, and source/drain features of the second transistor have the first conductivity type.

公开(公告)号：US20240047561A1

公开(公告)日：2024-02-08

申请号：US17882047

申请日：2022-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ta-Chun LIN ,  Ming-Che CHEN ,  Chun-Jun LIN ,  Kuo-Hua PAN ,  Jhon Jhy LIAW

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/7851 ,  H01L29/0847

Abstract: A method includes forming a semiconductor fin over a substrate; forming isolation structures laterally surrounding the semiconductor fin; forming a gate structure over the semiconductor fin; forming a first spacer layer and a second spacer layer over the gate structure and the semiconductor fin; etching back the second spacer layer, such that a top surface of the second spacer layer is lower than a top surface of the first spacer layer; after etching back the second spacer layer, forming a third spacer layer over the first spacer layer and the second spacer layer; etching the first, second, and third spacer layers and the semiconductor fin to form recesses; and forming epitaxial source/drain structures in the recesses.