公开(公告)号：US20240055048A1

公开(公告)日：2024-02-15

申请号：US18362736

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US20220359001A1

公开(公告)日：2022-11-10

申请号：US17814700

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US20190385672A1

公开(公告)日：2019-12-19

申请号：US16415554

申请日：2019-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US12119052B2

公开(公告)日：2024-10-15

申请号：US18362736

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US20230377614A1

公开(公告)日：2023-11-23

申请号：US18357769

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Qing Dong ,  Mahmut Sinangil ,  Yen-Ting Lin ,  Kerem Akarvardar ,  Carlos H. Diaz ,  Yih Wang

IPC: G11C7/08 ,  G11C7/10 ,  G11C16/26 ,  G11C5/06

CPC classification number: G11C7/08 ,  G11C7/1012 ,  G11C16/26 ,  G11C5/06 ,  G11C13/004

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

公开(公告)号：US11763882B2

公开(公告)日：2023-09-19

申请号：US17814700

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US11735235B2

公开(公告)日：2023-08-22

申请号：US17571077

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Qing Dong ,  Mahmut Sinangil ,  Yen-Ting Lin ,  Kerem Akarvardar ,  Carlos H. Diaz ,  Yih Wang

IPC: G11C7/06 ,  G11C7/14 ,  G11C11/56 ,  G11C7/08 ,  G11C7/10 ,  G11C16/26 ,  G11C5/06 ,  G11C13/00

CPC classification number: G11C7/08 ,  G11C5/06 ,  G11C7/1012 ,  G11C16/26 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0054

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

公开(公告)号：US20220130435A1

公开(公告)日：2022-04-28

申请号：US17571077

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Qing Dong ,  Mahmut Sinangil ,  Yen-Ting Lin ,  Kerem Akarvardar ,  Carlos H. Diaz ,  Yih Wang

IPC: G11C7/08 ,  G11C7/10 ,  G11C16/26 ,  G11C5/06

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

公开(公告)号：US20210043252A1

公开(公告)日：2021-02-11

申请号：US17068150

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US10803928B2

公开(公告)日：2020-10-13

申请号：US16415554

申请日：2019-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC: G11C11/419 ,  G11C11/418

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.