公开(公告)号：US20240064950A1

公开(公告)日：2024-02-22

申请号：US17890762

申请日：2022-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang ,  Yi-Feng Ting ,  Hsin-Wen Su ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

公开(公告)号：US20230197802A1

公开(公告)日：2023-06-22

申请号：US17832597

申请日：2022-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui-Lin Chen ,  Chao-Hsun Wang ,  Hsin-Wen Su ,  Yi-Feng Ting ,  Chi Hua Wang ,  I-Hung Li ,  Yuan-Tien Tu ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Ping-Wei Wang ,  Lien Jung Hung

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8238

CPC classification number: H01L29/41775 ,  H01L27/0886 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/42392

Abstract: A method according to the present disclosure includes forming a fin-shaped structure protruding from a substrate, forming a gate structure intersecting the fin-shaped structure, forming a gate spacer on a sidewall of the gate structure, and forming a conductive feature above the fin-shaped structure. The gate spacer is laterally between the gate structure and the conductive feature. The method also includes depositing a dielectric layer over the gate structure and the conductive feature, performing an etching process, thereby forming an opening through the dielectric layer and exposing top surfaces of the conductive feature and the gate structure, recessing the gate spacers through the opening, thereby exposing the sidewall of the gate structure, and forming a contact feature in the opening, wherein the contact feature is in contact with the conductive feature and has a bottom portion protruding downward to be in contact with the sidewall of the gate structure.

公开(公告)号：US20240395665A1

公开(公告)日：2024-11-28

申请号：US18469801

申请日：2023-09-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Feng-Ming Chang ,  Yung-Ting Chang ,  Ping-Wei Wang ,  Yi-Feng Ting

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.