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    Memory Device With Jogged Backside Metal Lines
    1.
    发明公开
    Memory Device With Jogged Backside Metal Lines 审中-公开

    公开(公告)号：US20240064950A1

    公开(公告)日：2024-02-22

    申请号：US17890762

    申请日：2022-08-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang ,  Yi-Feng Ting ,  Hsin-Wen Su ,  Lien-Jung Hung ,  Ping-Wei Wang

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1104

    摘要： A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

    Stable SRAM cell
    2.
    发明授权
    Stable SRAM cell 有权

    公开(公告)号：US08908409B2

    公开(公告)日：2014-12-09

    申请号：US14285410

    申请日：2014-05-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C15/00 ,  G11C11/412

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    Stable SRAM Cell
    3.
    发明申请
    Stable SRAM Cell 有权

    公开(公告)号：US20140254248A1

    公开(公告)日：2014-09-11

    申请号：US14285410

    申请日：2014-05-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Huai-Ying Huang ,  Yu-Kuan Lin ,  Sheng Chiang Hung ,  Feng-Ming Chang ,  Jui-Lin Chen ,  Ping-Wei Wang

    IPC分类号： G11C11/412

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

    INTERCONNECT STRUCTURES FOR INTEGRATION OF MEMORY CELLS AND LOGIC CELLS
    4.
    发明公开
    INTERCONNECT STRUCTURES FOR INTEGRATION OF MEMORY CELLS AND LOGIC CELLS 审中-公开

    公开(公告)号：US20240306362A1

    公开(公告)日：2024-09-12

    申请号：US18446576

    申请日：2023-08-09

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC分类号： H10B10/00

    CPC分类号： H10B10/18 ,  H10B10/125

    摘要： A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

    MULTI-PORT SRAM STRUCTURES WITH CELL SIZE OPTIMIZATION
    5.
    发明公开
    MULTI-PORT SRAM STRUCTURES WITH CELL SIZE OPTIMIZATION 审中-公开

    公开(公告)号：US20240304240A1

    公开(公告)日：2024-09-12

    申请号：US18351140

    申请日：2023-07-12

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/00

    CPC分类号： G11C11/412 ,  G11C11/419 ,  H10B10/12 ,  H10B10/18

    摘要： A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.

    INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCE
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH REDUCED VIA RESISTANCE 有权

    公开(公告)号：US20230062162A1

    公开(公告)日：2023-03-02

    申请号：US17461322

    申请日：2021-08-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jui-Lin Chen ,  Yu-Kuan Lin ,  Ping-Wei Wang

    IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/088

    摘要： A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.

    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES
    9.
    发明公开
    MULTI-PORT SRAM CELL WITH METAL INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20240306359A1

    公开(公告)日：2024-09-12

    申请号：US18364842

    申请日：2023-08-03

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Ping-Wei Wang ,  Feng-Ming Chang ,  Jui-Lin Chen

    IPC分类号： H10B10/00

    CPC分类号： H10B10/125

    摘要： A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.