公开(公告)号：US20240371972A1

公开(公告)日：2024-11-07

申请号：US18771887

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Jing-Yi Lin ,  Shang-Rong Li ,  Chong-De Lien

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

公开(公告)号：US20240347642A1

公开(公告)日：2024-10-17

申请号：US18755281

申请日：2024-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chong-De Lien ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Ming-Shuan Li ,  Hsin-Wen Su

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

公开(公告)号：US12040405B2

公开(公告)日：2024-07-16

申请号：US17319783

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chong-De Lien ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Ming-Shuan Li ,  Hsin-Wen Su

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78696 ,  H10B10/125

Abstract: A method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. In some embodiments, the method further includes forming a gate structure over the fin. Thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. In some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. In various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.

公开(公告)号：US11792977B2

公开(公告)日：2023-10-17

申请号：US17320049

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Wen Su ,  Shih-Hao Lin ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: A semiconductor device includes a program word line and a read word line over an active region. Each of the program word line and the read word line extends along a line direction. Moreover, the program word line engages a first transistor channel and the read word line engages a second transistor channel. The semiconductor device also includes a first metal line over and electrically connected to the program word line and a second metal line over and electrically connected to the read word line. The semiconductor device further includes a bit line over and electrically connected to the first active region. Additionally, the program word line has a first width along a channel direction perpendicular to the line direction; the read word line has a second width along the channel direction; and the first width is less than the second width.

公开(公告)号：US20220336480A1

公开(公告)日：2022-10-20

申请号：US17854809

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Yu-Kuan Lin ,  Shih-Hao Lin

IPC: H01L27/112 ,  G11C17/14 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/525

Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

公开(公告)号：US20220173098A1

公开(公告)日：2022-06-02

申请号：US17673030

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/423

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

公开(公告)号：US12022664B2

公开(公告)日：2024-06-25

申请号：US17408145

申请日：2021-08-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui-Lin Chen ,  Chenchen Jacob Wang ,  Hsin-Wen Su ,  Ping-Wei Wang ,  Yuan-Hao Chang ,  Po-Sheng Lu ,  Shih-Hao Lin

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

公开(公告)号：US11742416B2

公开(公告)日：2023-08-29

申请号：US17332025

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chia-Hung Chou ,  Chih-Hsuan Chen ,  Ping-En Cheng ,  Hsin-Wen Su ,  Chien-Chih Lin ,  Szu-Chi Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/7851

Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

公开(公告)号：US20230165160A1

公开(公告)日：2023-05-25

申请号：US17832601

申请日：2022-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Wen Su ,  Jui-Lin Chen ,  Shih-Hao Lin ,  Chih-Chuan Yang ,  Ming-Yen Chuang ,  Chenchen Jacob Wang ,  Ping-Wei Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/12

Abstract: Some embodiments relate to a memory device. The memory device includes a transistor having a first source/drain (S/D) region and a second S/D region, a first S/D contact disposed over the first S/D region, the first S/D contact extending lengthwise in a first direction, a second S/D contact disposed over the second S/D region, a first via landing on the first S/D contact, the first via extending lengthwise in a second direction different from the first direction, a second via landing on the second S/D contact, the first via having a length measured in the second direction that is larger than the second via, a first conductive line coupled to the first via, a second conductive line coupled to the second via, and a memory structure disposed above the transistor and coupled to the second conductive line.

公开(公告)号：US12218227B2

公开(公告)日：2025-02-04

申请号：US18447932

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chia-Hung Chou ,  Chih-Hsuan Chen ,  Ping-En Cheng ,  Hsin-Wen Su ,  Chien-Chih Lin ,  Szu-Chi Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.