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公开(公告)号：US11805661B2
公开(公告)日：2023-10-31
申请号：US17241071
申请日：2021-04-27
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu Bao , Hengyuan Lee , Ying-Yu Chen
CPC classification number: H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20200126893A1
公开(公告)日：2020-04-23
申请号：US16717136
申请日：2019-12-17
Inventor： Chih-Horng Chang , Jie-Cheng Deng , Tin-Hao Kuo , Ying-Yu Chen
Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
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公开(公告)号：US10522444B2
公开(公告)日：2019-12-31
申请号：US13895099
申请日：2013-05-15
Inventor： Chih-Horng Chang , Jie-Cheng Deng , Tin-Hao Kuo , Ying-Yu Chen
Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
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公开(公告)号：US12114512B2
公开(公告)日：2024-10-08
申请号：US18358035
申请日：2023-07-25
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu Bao , Hengyuan Lee , Ying-Yu Chen
CPC classification number: H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US12035542B2
公开(公告)日：2024-07-09
申请号：US18472235
申请日：2023-09-22
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu Bao , Hengyuan Lee , Ying-Yu Chen
CPC classification number: H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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Patent Agency Ranking
公开(公告)号：US20240015988A1
公开(公告)日：2024-01-11
申请号：US18472235
申请日：2023-09-22
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu BAO , Hengyuan Lee , Ying-Yu Chen
CPC classification number: H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20220069012A1
公开(公告)日：2022-03-03
申请号：US17241071
申请日：2021-04-27
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu BAO , Hengyuan Lee , Ying-Yu Chen
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20140252614A1
公开(公告)日：2014-09-11
申请号：US13895099
申请日：2013-05-15
Inventor： Chih-Horng Chang , Jie-Cheng Deng , Tin-Hao Kuo , Ying-Yu Chen
CPC classification number: H01L23/48 , H01L21/561 , H01L21/563 , H01L23/3128 , H01L23/3142 , H01L24/13 , H01L24/16 , H01L24/83 , H01L24/97 , H01L2224/13101 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/83051 , H01L2224/92125 , H01L2224/97 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2924/014 , H01L2924/00 , H01L2224/81 , H01L2224/83
Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
Abstract translation: 提供表面处理和半导体封装装置。 在一个实施例中，处理导电层的表面以产生粗糙表面。 在一个实例中，在导电层的表面上形成纳米线。 在铜导电层的情况下，纳米线可以包括CuO层。 在另一个实例中，在导电层的表面上形成复合化合物。 络合物可以使用例如硫醇和亚磷酸三甲酯形成。
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公开(公告)号：US20240373651A1
公开(公告)日：2024-11-07
申请号：US18772240
申请日：2024-07-14
Inventor： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien WU , Xinyu BAO , Hengyuan Lee , Ying-Yu Chen
Abstract: A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20220415968A1
公开(公告)日：2022-12-29
申请号：US17669313
申请日：2022-02-10
Inventor： Chien-Min Lee , Cheng-Hsien Wu , Cheng-Chun Chang , Elia Ambrosi , Hengyuan Lee , Ying-Yu Chen , Xinyu BAO , Tung-Ying Lee
Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.
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