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公开(公告)号：US12114512B2
公开(公告)日：2024-10-08
申请号：US18358035
申请日：2023-07-25
发明人： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu Bao , Hengyuan Lee , Ying-Yu Chen
CPC分类号： H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
摘要： A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US12041790B2
公开(公告)日：2024-07-16
申请号：US18161908
申请日：2023-01-31
发明人： Yu-Chao Lin , Tung-Ying Lee , Yuan-Tien Tu , Jung-Piao Chiu
CPC分类号： H10B63/24 , H10N70/068 , H10N70/8265 , H10N70/841 , H10N70/881
摘要： A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.
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公开(公告)号：US12035542B2
公开(公告)日：2024-07-09
申请号：US18472235
申请日：2023-09-22
发明人： Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Xinyu Bao , Hengyuan Lee , Ying-Yu Chen
CPC分类号： H10B63/24 , H10B63/80 , H10N70/011 , H10N70/231
摘要： A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.
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公开(公告)号：US20240196762A1
公开(公告)日：2024-06-13
申请号：US18582551
申请日：2024-02-20
发明人： Chen-Feng Hsu , Chien-Min Lee , Tung-Ying Lee , Cheng-Hsien Wu , Hengyuan Lee , Xinyu BAO
CPC分类号： H10N70/231 , H10B63/30 , H10N70/021 , H10N70/061 , H10N70/841 , H10N70/8825 , H10N70/8828
摘要： A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.
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公开(公告)号：US11968844B2
公开(公告)日：2024-04-23
申请号：US17981469
申请日：2022-11-06
发明人： Chien-Min Lee , Ming-Yuan Song , Yen-Lin Huang , Shy-Jay Lin , Tung-Ying Lee , Xinyu Bao
CPC分类号： H10B61/22 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , H10N52/00 , H10N52/01 , H10N52/80
摘要： Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
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公开(公告)号：US11864477B2
公开(公告)日：2024-01-02
申请号：US17730235
申请日：2022-04-27
发明人： Yu-Chao Lin , Tung-Ying Lee
CPC分类号： H10N70/8828 , H10N70/061 , H10N70/231 , H10N70/841
摘要： Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided.
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公开(公告)号：US11756645B2
公开(公告)日：2023-09-12
申请号：US17408500
申请日：2021-08-23
发明人： Win-San Khwa , Jen-Chieh Liu , Meng-Fan Chang , Tung-Ying Lee , Jin Cai
CPC分类号： G11C29/42 , G11C16/102 , G11C16/26 , G11C29/4401 , G11C2029/1208
摘要： A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.
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公开(公告)号：US20230180486A1
公开(公告)日：2023-06-08
申请号：US18161908
申请日：2023-01-31
发明人： Yu-Chao Lin , Tung-Ying Lee , Yuan-Tien Tu , Jung-Piao Chiu
CPC分类号： H10B63/24 , H10N70/068 , H10N70/841 , H10N70/881 , H10N70/8265
摘要： A memory cell includes a bottom electrode, a memory element, spacers, a selector and a top electrode. The memory element is located on the bottom electrode and includes a first conductive layer, a second conductive layer and a storage layer. The first conductive layer is electrically connected to the bottom electrode. The second conductive layer is located on the first conductive layer, wherein a width of the first conductive layer is smaller than a width of the second conductive layer. The storage layer is located in between the first conductive layer and the second conductive layer. The spacers are located aside the second conductive layer and the storage layer. The selector is disposed on the spacers and electrically connected to the memory element. The top electrode is disposed on the selector.
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公开(公告)号：US11616146B2
公开(公告)日：2023-03-28
申请号：US17729333
申请日：2022-04-26
发明人： Yu-Chao Lin , Wei-Sheng Yun , Tung-Ying Lee
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.
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公开(公告)号：US20230071950A1
公开(公告)日：2023-03-09
申请号：US17981469
申请日：2022-11-06
发明人： Chien-Min Lee , Ming-Yuan Song , Yen-Lin Huang , Shy-Jay Lin , Tung-Ying Lee , Xinyu BAO
摘要： Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
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