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公开(公告)号：US10825892B2
公开(公告)日：2020-11-03
申请号：US16741058
申请日：2020-01-13
IPC分类号： H01L49/02
摘要： A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
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公开(公告)号：US10686060B2
公开(公告)日：2020-06-16
申请号：US16443184
申请日：2019-06-17
IPC分类号： H01L29/66 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/49 , H01L29/51 , H01L21/311 , H01L21/762
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.
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公开(公告)号：US20190305115A1
公开(公告)日：2019-10-03
申请号：US16443184
申请日：2019-06-17
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L21/8238 , H01L29/49 , H01L21/762 , H01L21/311 , H01L27/092 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/06
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element
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公开(公告)号：US10014394B2
公开(公告)日：2018-07-03
申请号：US15414449
申请日：2017-01-24
IPC分类号： H01L21/762 , H01L29/66 , H01L21/311
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.
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公开(公告)号：US10008559B2
公开(公告)日：2018-06-26
申请号：US15420660
申请日：2017-01-31
IPC分类号： H01L49/02
CPC分类号： H01L28/60 , H01L28/55 , H01L2224/11
摘要： A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
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公开(公告)号：US20180174925A1
公开(公告)日：2018-06-21
申请号：US15898910
申请日：2018-02-19
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/66 , H01L29/51 , H01L29/49 , H01L29/423 , H01L29/267 , H01L29/24 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/08 , H01L29/06 , H01L27/092
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element
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公开(公告)号：US20170084499A1
公开(公告)日：2017-03-23
申请号：US15368322
申请日：2016-12-02
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/06 , H01L29/51 , H01L29/08 , H01L29/66 , H01L29/16 , H01L29/165 , H01L29/24 , H01L29/267 , H01L27/092 , H01L29/78 , H01L29/161
CPC分类号： H01L29/66795 , H01L21/31111 , H01L21/76224 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/0924 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/42372 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element
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公开(公告)号：US10854505B2
公开(公告)日：2020-12-01
申请号：US15405391
申请日：2017-01-13
IPC分类号： H01L21/768
摘要： A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
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公开(公告)号：US20170278742A1
公开(公告)日：2017-09-28
申请号：US15405391
申请日：2017-01-13
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76877
摘要： A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
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公开(公告)号：US11171040B2
公开(公告)日：2021-11-09
申请号：US16204088
申请日：2018-11-29
IPC分类号： H01L21/768
摘要： A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.
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