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公开(公告)号：US20230337436A1
公开(公告)日：2023-10-19
申请号：US18338344
申请日：2023-06-21
发明人： Meng-Han Lin , Chun-Fu Cheng , Feng-Cheng Yang , Sheng-Chen Wang , Yu-Chien Chiu , Han-Jong Chia
摘要： A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.
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公开(公告)号：US20240113234A1
公开(公告)日：2024-04-04
申请号：US18149715
申请日：2023-01-04
发明人： Ya-Yun Cheng , Wen-Ling Lu , Yu-Chien Chiu , Chung-Wei Wu , Zhiqiang Wu
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/24
摘要： An integrated chip including a gate layer. An insulator layer is over the gate layer. A channel structure is over the insulator layer. A pair of source/drains are over the channel structure and laterally spaced apart by a dielectric layer. The channel structure includes a first channel layer between the insulator layer and the pair of source/drains, a second channel layer between the insulator layer and the dielectric layer, and a third channel layer between the second channel layer and the dielectric layer. The first channel layer, the second channel layer, and the third channel layer include different semiconductors.
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公开(公告)号：US11723209B2
公开(公告)日：2023-08-08
申请号：US17159120
申请日：2021-01-26
发明人： Meng-Han Lin , Chun-Fu Cheng , Feng-Cheng Yang , Sheng-Chen Wang , Yu-Chien Chiu , Han-Jong Chia
摘要： A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.
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公开(公告)号：US11716857B2
公开(公告)日：2023-08-01
申请号：US17351121
申请日：2021-06-17
发明人： Yu-Chien Chiu , Meng-Han Lin , Chun-Fu Cheng , Han-Jong Chia , Chung-Wei Wu , Zhiqiang Wu
CPC分类号： H10B51/20 , H01L29/0649 , H10B51/10 , H10B51/30
摘要： A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.
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公开(公告)号：US20210375938A1
公开(公告)日：2021-12-02
申请号：US17159120
申请日：2021-01-26
发明人： Meng-Han Lin , Chun-Fu Cheng , Feng-Cheng Yang , Sheng-Chen Wang , Yu-Chien Chiu , Han-Jong Chia
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11582
摘要： A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.
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