Three-dimensional memory device and manufacturing method thereof

    公开(公告)号:US11723209B2

    公开(公告)日:2023-08-08

    申请号:US17159120

    申请日:2021-01-26

    IPC分类号: H10B51/20 H10B43/27 H10B51/30

    CPC分类号: H10B51/20 H10B43/27 H10B51/30

    摘要: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars are separately located within the cell regions, and are laterally surrounded by the channel layers.

    Semiconductor Structures and Methods Thereof

    公开(公告)号:US20220278198A1

    公开(公告)日:2022-09-01

    申请号:US17187458

    申请日:2021-02-26

    摘要: In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon.

    Doping for FinFET
    8.
    发明申请
    Doping for FinFET 有权
    掺杂FinFET

    公开(公告)号:US20150243739A1

    公开(公告)日:2015-08-27

    申请号:US14186910

    申请日:2014-02-21

    摘要: First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin.

    摘要翻译: 从基板形成第一和第二散热片。 第一层形成在第一鳍上。 第一层包括第一掺杂剂。 第一层的一部分从第一鳍片的尖端部分去除。 第二层形成在第二鳍上。 第二层包括第二掺杂剂。 第一和第二掺杂剂之一是p型掺杂剂,第一和第二掺杂剂中的另一种是n型掺杂剂。 第二层的一部分从第二鳍的尖端部分移除。 执行固相扩散处理以将第一掺杂剂扩散到第一鳍片的非尖端部分中,并将第二掺杂剂扩散到第二鳍片的非尖端部分。

    Semiconductor device with improved source and drain contact area and methods of fabrication thereof

    公开(公告)号:US11476342B1

    公开(公告)日:2022-10-18

    申请号:US17308617

    申请日:2021-05-05

    摘要: Semiconductor device includes substrate having fins, first S/D feature comprising first epitaxial layer contacting first fin, second epitaxial layer on first epitaxial layer, third epitaxial layer on second epitaxial layer, third epitaxial layer comprising center and edge portion higher than center portion, and fourth epitaxial layer on third epitaxial layer, second S/D feature adjacent first S/D feature and comprising first epitaxial layer contacting second fin, second epitaxial layer on first epitaxial layer of second S/D feature, third epitaxial layer on second epitaxial layer of second S/D feature, third epitaxial layer comprising center and edge portion higher than center portion of third epitaxial layer, center and edge portions of third epitaxial layer of first and second S/D features are merging, and fourth epitaxial layer on third epitaxial layer of second S/D feature, S/D contact covering edge and center portions of third epitaxial layers of first and second S/D features.