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公开(公告)号：US12063787B2
公开(公告)日：2024-08-13
申请号：US18155688
申请日：2023-01-17
发明人： Sheng-Chen Wang , Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin , Han-Jong Chia
IPC分类号： H10B51/20 , H01L29/417 , H10B51/00 , H10B51/10 , H10B51/30
CPC分类号： H10B51/20 , H01L29/41741 , H01L29/41775 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
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公开(公告)号：US12058867B2
公开(公告)日：2024-08-06
申请号：US17086463
申请日：2020-11-02
发明人： Chao-I Wu , Han-Jong Chia , Yu-Ming Lin , Sai-Hooi Yeong
IPC分类号： H01L29/78 , H01L21/28 , H01L23/522 , H01L29/51 , H01L29/66 , H10B51/10 , H10B51/20 , H10B51/30
CPC分类号： H10B51/10 , H01L23/5226 , H01L29/40111 , H01L29/516 , H01L29/66666 , H01L29/78391 , H10B51/20 , H10B51/30
摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
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公开(公告)号：US20240215255A1
公开(公告)日：2024-06-27
申请号：US18602041
申请日：2024-03-12
发明人： Han-Jong Chia , Meng-Han Lin , Yu-Ming Lin
CPC分类号： H10B51/20 , G11C11/2255 , G11C11/2257 , H10B51/10 , H10B51/40
摘要： A memory device including a word line, memory cells, source lines and bit lines is provided. The memory cells are embedded in and penetrate through the word line. The source lines and the bit lines are electrically connected the memory cells. A method for fabricating a memory device is also provided.
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公开(公告)号：US20240147732A1
公开(公告)日：2024-05-02
申请号：US18404064
申请日：2024-01-04
发明人： Chao-I Wu , Yu-Ming Lin , Han-Jong Chia
CPC分类号： H10B53/00 , G11C5/06 , G11C11/221 , H10B51/00
摘要： A semiconductor structure includes a substrate, an interconnection structure disposed over the substrate and a first memory cell. The first memory cell is disposed over the substrate and embedded in dielectric layers of the interconnection structure. The first memory cell includes a first transistor and a first data storage structure. The first transistor is disposed on a first base dielectric layer and embedded in a first dielectric layer. The first data storage structure is embedded in a second dielectric layer and electrically connected to the first transistor. The first data storage structure includes a first electrode, a second electrode and a storage layer sandwiched between the first electrode and the second electrode.
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公开(公告)号：US11915787B2
公开(公告)日：2024-02-27
申请号：US17815113
申请日：2022-07-26
发明人： Bo-Feng Young , Yu-Ming Lin , Shih-Lien Linus Lu , Han-Jong Chia , Sai-Hooi Yeong , Chia-En Huang , Yih Wang
摘要： An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.
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6.发明公开公开(公告)号：US20240055519A1
公开(公告)日：2024-02-15
申请号：US18493856
申请日：2023-10-25
发明人： Han-Jong Chia
CPC分类号： H01L29/78391 , H01L29/516 , H01L29/0649 , G11C11/223 , H01L29/517 , H01L21/0228 , H01L29/6656
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a switching layer over a semiconductor substrate. The switching layer comprises a first metal oxide. An upper conductive structure overlies the switching layer. The switching layer is spaced between opposing sidewalls of the upper conductive structure. A first dielectric layer is disposed along opposing sidewalls of the switching layer. The first dielectric layer comprises a second metal oxide different from the first metal oxide. A top surface of the switching layer and a top surface of the first dielectric layer directly underlie a bottom surface of the upper conductive structure.
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公开(公告)号：US11864393B2
公开(公告)日：2024-01-02
申请号：US18156734
申请日：2023-01-19
CPC分类号： H10B63/30 , G11C13/003 , G11C13/0007 , G11C13/0097 , H10B63/845 , H10N70/066 , H10N70/24 , G11C2213/79
摘要： A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.
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公开(公告)号：US11832450B2
公开(公告)日：2023-11-28
申请号：US17867998
申请日：2022-07-19
发明人： Bo-Feng Young , Chung-Te Lin , Sai-Hooi Yeong , Yu-Ming Lin , Sheng-Chih Lai , Chih-Yu Chang , Han-Jong Chia
CPC分类号： H10B51/30 , G11C11/223 , H01L27/1211
摘要： Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.
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公开(公告)号：US11830550B2
公开(公告)日：2023-11-28
申请号：US17392830
申请日：2021-08-03
发明人： Han-Jong Chia , Sai-Hooi Yeong , Yu-Ming Lin
CPC分类号： G11C14/0072 , G11C11/221 , G11C11/223 , G11C11/2259 , G11C11/2275 , G11C11/419 , H10B10/12 , H10B51/30 , H10B53/30
摘要： Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.
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公开(公告)号：US20230371274A1
公开(公告)日：2023-11-16
申请号：US18357153
申请日：2023-07-23
发明人： Han-Jong Chia
CPC分类号： H10B53/30 , H01L21/3115 , H01L28/60 , H01L29/40111 , H01L29/6684 , H01L29/78391 , H10B51/30
摘要： A ferroelectric memory device includes a first conductive region, a second conductive region and a ferroelectric structure. The second conductive region is disposed over the first conductive region. The ferroelectric structure includes a plurality of different ferroelectric materials stacked between the first conductive region and the second conductive region.
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