公开(公告)号：US06216194B1

公开(公告)日：2001-04-10

申请号：US09210482

申请日：1998-12-14

申请人： Takaharu Aoyama ,  Toshimi Sugita ,  Tsuyoshi Katoh ,  Hirokatsu Shioda ,  Kazuo Sugai ,  Nobuhito Matsuyama

发明人： Takaharu Aoyama ,  Toshimi Sugita ,  Tsuyoshi Katoh ,  Hirokatsu Shioda ,  Kazuo Sugai ,  Nobuhito Matsuyama

IPC分类号： G06F1300

CPC分类号： G06F13/4027

摘要： An information processing unit having a bus controller connected to a plurality of different shared buses which can independently control the different shared buses, and a double adaptor connected to the different shared buses which can independently control the different shared buses, wherein first and second ones of the shared buses are independently controlled to send data from the bus controller to the double adaptor, and from the double adaptor to the bus controller, respectively.

摘要翻译： 一种信息处理单元，其具有连接到可以独立地控制不同共享总线的多个不同共享总线的总线控制器，以及连接到不同共享总线的双适配器，其可以独立地控制不同的共享总线，其中第一和第二 共享总线被独立控制，以将数据从总线控制器发送到双适配器，并分别从双适配器发送到总线控制器。

公开(公告)号：US07397765B2

公开(公告)日：2008-07-08

申请号：US10769082

申请日：2004-01-30

申请人： Takeshi Aimoto ,  Nobuhito Matsuyama ,  Kazuo Sugai ,  Hiroki Yano ,  Yoshihiko Sakata ,  Shinichi Akahane ,  Yuichi Ishikawa

发明人： Takeshi Aimoto ,  Nobuhito Matsuyama ,  Kazuo Sugai ,  Hiroki Yano ,  Yoshihiko Sakata ,  Shinichi Akahane ,  Yuichi Ishikawa

IPC分类号： H04L1/00

CPC分类号： H04L47/32 ,  H04L47/10 ,  H04L47/11 ,  H04L47/20 ,  H04L47/2408 ,  H04L47/283 ,  H04L47/36

摘要： In one embodiment, a bandwidth monitoring device comprises a packet receiving circuit configured to receive packets; a counter configured to count a total packet length by adding up inputted packet lengths including a packet length of a next input packet and subtracting outputted packet lengths to produce a counted value; a timer configured to time a packet receiving time; a memory configured to store a number of packet receiving times and a number of counted values counted by the counter which correspond to the packet receiving times, respectively; a counter rate-of-change calculating portion configured to calculate a change rate by a first counted value corresponding to an oldest packet receiving time stored in the memory representing an oldest time at which a packet was received and a second counted value corresponding to a latest packet receiving time stored in the memory representing a latest time at which a packet was received; and a determining portion configured to decide whether the next input packet will be discarded based on a probability computed by the change rate and the counted value counted by the counter when the packet receiving circuit receives the next input packet.

摘要翻译： 在一个实施例中，带宽监视设备包括被配置为接收分组的分组接收电路; 配置为通过将包括下一个输入分组的分组长度的输入分组长度相加并减去输出的分组长度以产生计数值来计数总分组长度; 定时器，配置为对分组接收时间进行计时; 存储器，被配置为分别存储与所述分组接收时间对应的由所述计数器计数的多个分组接收时间和多个计数值; 计数变化率计算部分，被配置为计算与存储在表示接收到分组的最旧时间的存储器中的最旧的分组接收时间相对应的第一计数值的变化率，以及对应于最新的 分组接收时间存储在存储器中，表示接收到分组的最新时间; 以及确定部分，被配置为基于当分组接收电路接收到下一个输入分组时由所述改变率计算的概率和由所述计数器计数的计数值来决定下一个输入分组是否将被丢弃。

公开(公告)号：US06768738B1

公开(公告)日：2004-07-27

申请号：US09393326

申请日：1999-09-10

申请人： Takeki Yazaki ,  Takeshi Aimoto ,  Kazuo Sugai ,  Nobuhito Matsuyama

发明人： Takeki Yazaki ,  Takeshi Aimoto ,  Kazuo Sugai ,  Nobuhito Matsuyama

IPC分类号： H04L1256

CPC分类号： H04L12/46 ,  H04L29/06 ,  H04L45/00 ,  H04L45/54 ,  H04L45/60 ,  H04L45/745 ,  H04L47/50 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/25 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9036 ,  H04L67/327 ,  H04L69/12 ,  H04L2012/5636 ,  H04Q11/0478

摘要： A packet forwarding apparatus provided with a plurality of line interface units, comprises a routing processing unit for referring to a routing table, based on header information of received packet to specify one of output lines to output the received packet, a flow detection unit for referring to an entry table, in which a plurality of entries with flow conditions and control information are registered, to retrieve control information defined by the entry with a flow condition which coincides with that of the header information of the received packet, and a packet forwarding unit for transferring the received packet to one of the line interface units connected to the output line specified by the routing processing unit. The entry table id divided into a plurality of subtables corresponding to the values of flow attributes associated with the received packets and the flow detection unit retrieves the control information from one of said subtables specified by the value of the flow attribute corresponding to the received packet.

摘要翻译： 具有多个线路接口单元的分组转发装置包括：路由处理单元，用于根据接收到的分组的头信息来参考路由表，以指定输出所述接收分组的输出行之一;流量检测单元，用于参考 将具有流量条件和控制信息的多个条目登记到条目表中，以检索由条目定义的控制信息，其中流程条件与接收到的分组的标题信息的流条件一致;以及分组转发单元 用于将接收到的分组传送到连接到由路由处理单元指定的输出线的线路接口单元之一。 入口表id被划分为与接收到的分组相关联的流属性的值对应的多个子表，并且流检测单元从与接收到的分组对应的流属性的值指定的所述子表之一中检索控制信息。

公开(公告)号：US06683885B1

公开(公告)日：2004-01-27

申请号：US09511798

申请日：2000-02-23

申请人： Kazuo Sugai ,  Takeshi Aimoto ,  Takeki Yazaki ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Tomohiko Tanabe

发明人： Kazuo Sugai ,  Takeshi Aimoto ,  Takeki Yazaki ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Tomohiko Tanabe

IPC分类号： H04L1256

CPC分类号： H04L45/00 ,  H04L45/583 ,  H04L45/60 ,  H04L49/205 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3063 ,  H04L49/309 ,  H04L49/9042 ,  H04L2012/5618

摘要： A network relaying apparatus and a network relaying method for securing a high communication quality (QoS), a high reliability and security. A transfer engine stores the packets received through at least a network interface in a packet buffer, and the header information in a header RAM. A search engine searches for the transfer control information such as the destination information and the action information based on the header information, and writes them in the header RAM. The transfer engine prepares an output packet based on the information stored in the packet buffer and the header RAM, and outputs the output packet to the destination. A switch switches the output packet to the routing processor of the destination. Each header RAM is asynchronously accessible independently of the packet buffer and suppresses the competition for access between the transfer engine and the search engine.

摘要翻译： 一种用于确保高通信质量（QoS），高可靠性和安全性的网络中继设备和网络中继方法。 传输引擎将通过至少网络接口接收的分组存储在分组缓冲器中，并且头部信息存储在头部RAM中。 搜索引擎基于头信息搜索诸如目的地信息和动作信息的传送控制信息，并将它们写入标题RAM。 传输引擎基于存储在分组缓冲器和头部RAM中的信息来准备输出分组，并将输出分组输出到目的地。 交换机将输出分组切换到目的地的路由处理器。 每个标题RAM是独立于分组缓冲区而异步访问的，并且抑制了传输引擎和搜索引擎之间的访问竞争。

公开(公告)号：US08774001B2

公开(公告)日：2014-07-08

申请号：US13357927

申请日：2012-01-25

申请人： Takeshi Kumagai ,  Nobuhito Matsuyama ,  Takeshi Aimoto ,  Toshio Doi ,  Kazuo Sugai

发明人： Takeshi Kumagai ,  Nobuhito Matsuyama ,  Takeshi Aimoto ,  Toshio Doi ,  Kazuo Sugai

IPC分类号： H04L12/26

CPC分类号： H04L47/6275 ,  H04L47/2441 ,  H04L47/60 ,  H04L49/9036

摘要： A relay device of relaying a communication packet is disclosed, which comprises: an input module configured to receive the communication packet as an input; a buffer configured to have a plurality of queues and temporarily accumulated the received communication packet; a sorter configured to sort the received communication packet to one of the plurality of queues, depending on a specific value obtained by a predetermined function that gives an aggregate output from an input which is transfer information regarding transfer of the communication packet; and a band controller configured to control a bandwidth for each of the plurality of queues and output communication packets accumulated in the plurality of queues for transmission of the communication packets. This ensures the quality of service, while saving the capacity of the buffer used for the queues.

摘要翻译： 公开了一种中继通信分组的中继装置，包括：输入模块，用于接收通信分组作为输入; 配置为具有多个队列并临时累积所接收的通信分组的缓冲器; 分拣机，被配置为根据通过给出来自关于通信分组的传送的传输的信息的输入的聚合输出的预定功能获得的特定值，将接收到的通信分组排序到多个队列中的一个队列; 以及频带控制器，被配置为控制所述多个队列中的每一个的带宽，并且输出在所述多个队列中累积的通信分组，以发送所述通信分组。 这确保了服务质量，同时节省了用于队列的缓冲区的容量。

公开(公告)号：US08139576B2

公开(公告)日：2012-03-20

申请号：US12202779

申请日：2008-09-02

申请人： Kazuo Sugai ,  Nobuhito Matsuyama

发明人： Kazuo Sugai ,  Nobuhito Matsuyama

IPC分类号： H04L12/56

CPC分类号： H04L45/60 ,  H04L45/00 ,  H04L45/30 ,  H04L45/583 ,  H04L69/22

摘要： A network routing apparatus in which packet forwarding units for performing a packet forwarding process are arranged in parallel to one another, a packet distribution unit for distributing packets to the packet forwarding units arranged in parallel to one another, a packet rearrangement unit for rearranging outputs of the packet forwarding units are provided in the network routing apparatus, and packet retrieving units for retrieving packet headers in the packet forwarding units are further arranged in parallel to one another.

摘要翻译： 一种网络路由设备，其中用于执行分组转发过程的分组转发单元彼此并行布置，分组分发单元，用于将分组分组到彼此并行布置的分组转发单元，分组重排单元，用于重新排列 分组转发单元被提供在网络路由设备中，并且用于在分组转发单元中检索分组报头的分组检索单元进一步彼此并行布置。

公开(公告)号：US06560233B1

公开(公告)日：2003-05-06

申请号：US09266635

申请日：1999-03-11

申请人： Satoshi Hatanaka ,  Nobuhito Matsuyama ,  Kazuo Sugai ,  Yukisada Yamakawa

发明人： Satoshi Hatanaka ,  Nobuhito Matsuyama ,  Kazuo Sugai ,  Yukisada Yamakawa

IPC分类号： H04J1226

CPC分类号： H04L49/3009 ,  H04L49/254 ,  H04L49/30

摘要： Each of a plurality of data processing units that form a network relaying apparatus has a memory controller, a network controller, a processor, and independently accessible first and second memories. The memory controller includes a header information register for storing header information such as a header start position in a packet and a header length; a header position detection circuit for detecting a header position in the packet based on the header information contained in the header information register; and an inter-data processing unit transfer circuit for sending and receiving a packet to and from another data processing unit. The data processing unit stores into the first memory a packet received from the network or a packet transferred from another data processing unit, and at the same time stores only a header portion of the packet into the second memory. The processor reads the header portion of the packet from the second memory and analyzes it while at the same time the network controller and the inter-data processing unit transfer circuit write and read another packet to and from the first memory.

摘要翻译： 形成网络中继装置的多个数据处理单元中的每一个具有存储器控制器，网络控制器，处理器和可独立存取的第一和第二存储器。 存储器控制器包括一个标题信息寄存器，用于存储诸如分组中的报头开始位置和报头长度的报头信息; 标题位置检测电路，用于基于包含在标题信息寄存器中的标题信息来检测分组中的报头位置; 以及用于向和从另一数据处理单元发送和接收分组的数据间处理单元传送电路。 数据处理单元将从网络接收的分组或从另一数据处理单元传送的分组存储到第一存储器中，并且同时仅将分组的报头部分存储到第二存储器中。 处理器从第二存储器读取分组的报头部分并对其进行分析，同时网络控制器和数据间处理单元传送电路向第一存储器写入和读取另一分组。

公开(公告)号：US06874033B1

公开(公告)日：2005-03-29

申请号：US09622484

申请日：1998-03-23

申请人： Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Shinichi Akahane ,  Noboru Tanabe ,  Yoshihito Sako

发明人： Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Shinichi Akahane ,  Noboru Tanabe ,  Yoshihito Sako

IPC分类号： G06F17/30 ,  H04L12/66 ,  H04L12/701 ,  H04L12/745 ,  G06F15/173

CPC分类号： H04L45/00 ,  H04L45/48 ,  H04L45/742

摘要： The present invention improves a network forwarding device, such as a router, in a computer network system. When an address to which a received packet is to be forwarded is searched for based on path information, a path search data structure is changed to the one in which, in a 2-branch tree search in which a destination address of the received packet is checked, one bit at a time beginning at a highest-order bit, p (p is an integer equal to or larger than 2) levels are combined into one 2P-branch tree to perform a search of the p levels of the 2-branch tree as a one-level search. This data structure speeds up path search processing.

摘要翻译： 本发明改进了计算机网络系统中的诸如路由器的网络转发设备。 当基于路径信息搜索要转发接收到的分组的地址时，将路径搜索数据结构改变为在其中所接收分组的目的地地址为2的分支树搜索中的路径搜索数据结构 检查，一个位从一个最高位开始，p（p是等于或大于2的整数）的级别被组合成一个2 分支树，以执行对p 2分支树作为一级搜索。 该数据结构加速了路径搜索处理。

公开(公告)号：US06778532B1

公开(公告)日：2004-08-17

申请号：US09389301

申请日：1999-09-02

申请人： Shinichi Akahane ,  Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Hiroshi Sekino

发明人： Shinichi Akahane ,  Kazuo Sugai ,  Takeshi Aimoto ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Hiroshi Sekino

IPC分类号： H04J110

CPC分类号： H04L45/742 ,  H04L12/18 ,  H04L12/46 ,  H04L45/00 ,  H04L45/16

摘要： In a high speed multicast route searching method of searching information of a transmission port to which a received multicast packet is next transferred: a route address is formed by coupling a receiver address and a sender address in this order; one p-th power-of-2-branch tree node is configured by a collection of one two-branch tree node and two-branch tree nodes of p−1 stages totalling ((p-th power of 2)−1) nodes just under the one two-branch tree node to form a p-th power-of-2-branch tree which is stored in a memory; not one bit but consecutive p bits of the route address coupling the receiver address and sender address in a received multicast packet in this order are checked at the same time; and in accordance with the values of the consecutive bits, a search tree stored in the memory is searched. In this manner, a search process can be completed by tracing nodes (the number of bits of a search key divided by p) times at a maximum, independently from the number of entries.

摘要翻译： 在高速多播路由搜索方法中，搜索接收到的多播分组的下一个传输的传输端口的信息：通过按照该顺序耦合接收机地址和发送方地址来形成路由地址; 一个p个2分支树状节点由一个两分支树节点和总共（（p-th功率为2）-1）个节点的p-1级的两分支树节点的集合来配置 恰好在一个双分支树节点之下，以形成存储在存储器中的第p个2分支树枝; 不是一个位，而是同时检查在接收到的组播数据包中按顺序耦合接收器地址和发送方地址的路由地址的连续p位; 并且根据连续比特的值，搜索存储在存储器中的搜索树。 以这种方式，可以独立于条目的数量，通过跟踪节点（搜索关键字的比特数除以p）乘以最大值来完成搜索处理。

公开(公告)号：US06671277B1

公开(公告)日：2003-12-30

申请号：US09511797

申请日：2000-02-23

申请人： Kazuo Sugai ,  Takeshi Aimoto ,  Takeki Yazaki ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Tomohiko Tanabe

发明人： Kazuo Sugai ,  Takeshi Aimoto ,  Takeki Yazaki ,  Nobuhito Matsuyama ,  Yoshihito Sako ,  Tomohiko Tanabe

IPC分类号： H04L1256

CPC分类号： H04L45/00 ,  H04L45/583 ,  H04L45/60 ,  H04L49/205 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3063 ,  H04L49/309 ,  H04L2012/5618

摘要： A network relaying apparatus and method for high quality transfer of packets under stable quality-of-service (QoS) control. A transfer engine stores the packets received through a network interface, in a packet buffer, and the header information in a RAM. A search engine searches the transfer control information including the transfer destination information and the action information according to the header information and writes the resulting information in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch operates to switch the output packet to the routing processor of the destination. The QoS control is performed at each of a plurality of points including the input-side routing processor, the output-side routing processor 10 and the switch.

摘要翻译： 一种用于在稳定的服务质量（QoS）控制下高质量传输数据包的网络中继设备和方法。 传输引擎将通过网络接口接收的分组存储在分组缓冲器中，并将报头信息存储在RAM中。 搜索引擎根据头信息搜索包括传送目的地信息和动作信息的传送控制信息，并将得到的信息写入标题RAM。 传输引擎基于存储在分组缓冲器和头部RAM中的信息产生输出分组，并将其输出到传送目的地。 交换机用于将输出分组切换到目的地的路由处理器。 在包括输入侧路由处理器，输出侧路由处理器10和交换机的多个点的每一个处执行QoS控制。