公开(公告)号：US20130228842A1

公开(公告)日：2013-09-05

申请号：US13601076

申请日：2012-08-31

申请人： Takahiro Kotou ,  Hideto Takekida ,  Minori Kajimoto

发明人： Takahiro Kotou ,  Hideto Takekida ,  Minori Kajimoto

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7889 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A semiconductor storage device includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. A charge storage layer includes a first part provided on the first insulating film, an intermediate insulating film provided on the first part, and a second part provided on the intermediate insulating film, and is capable of storing electric charges. A second insulating film is provided on an upper surface and a side surface of the charge storage layer. A control gate is opposed to the upper surface and the side surface of the charge storage layer via the second insulating film, and is configured to control a voltage of the charge storage layer. The intermediate insulating film is recessed in comparison with side surfaces of the first and second parts on the side surface of the charge storage layer.

摘要翻译： 半导体存储装置包括半导体基板。 第一绝缘膜设置在半导体衬底上。 电荷存储层包括设置在第一绝缘膜上的第一部分，设置在第一部分上的中间绝缘膜和设置在中间绝缘膜上的第二部分，并且能够存储电荷。 第二绝缘膜设置在电荷存储层的上表面和侧表面上。 控制栅极经由第二绝缘膜与电荷存储层的上表面和侧表面相对，并且被配置为控制电荷存储层的电压。 与电荷储存层的侧表面上的第一和第二部分的侧表面相比，中间绝缘膜凹陷。

公开(公告)号：US20120217571A1

公开(公告)日：2012-08-30

申请号：US13402477

申请日：2012-02-22

申请人： Fumitaka ARAI ,  Satoshi Nagashima ,  Hisataka Meguro ,  Hideto Takekida ,  Kenta Yamada

发明人： Fumitaka ARAI ,  Satoshi Nagashima ,  Hisataka Meguro ,  Hideto Takekida ,  Kenta Yamada

IPC分类号： H01L29/792 ,  H01L21/76

CPC分类号： H01L27/11524 ,  G11C16/0466 ,  H01L27/11551 ,  H01L29/66825 ,  H01L29/7881

摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。 第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。 第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。 第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。 第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。 控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。 控制门在垂直于第一方向的第二方向延伸。

公开(公告)号：US20120175695A1

公开(公告)日：2012-07-12

申请号：US13336398

申请日：2011-12-23

申请人： Yuichi SATO ,  Hideto Takekida

发明人： Yuichi SATO ,  Hideto Takekida

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L27/11524

摘要： A semiconductor storage device according to an embodiment includes a memory cell comprising a charge accumulate layer above a semiconductor substrate and a control gate above the charge accumulate layer. The charge accumulate layer is capable of accumulating charges therein. The control gate is configured to control an amount of the charges accumulated in the charge accumulate layer. The control gate comprises a lower-layer control gate part of metal or metallic silicide which is processable by etching, and an upper-layer control gate part of a material different from that of the lower-layer control gate part.

摘要翻译： 根据实施例的半导体存储装置包括存储单元，其包括半导体衬底上方的电荷累积层和电荷累积层上方的控制栅极。 电荷积聚层能够在其中积累电荷。 控制栅极被配置为控制在电荷累积层中累积的电荷的量。 控制栅极包括可通过蚀刻处理的金属或金属硅化物的下层控制栅极部分和与下层控制栅极部分不同的材料的上层控制栅极部分。

公开(公告)号：US08952444B2

公开(公告)日：2015-02-10

申请号：US13398208

申请日：2012-02-16

申请人： Hideto Takekida

发明人： Hideto Takekida

IPC分类号： H01L21/764 ,  H01L21/762 ,  H01L27/115

CPC分类号： H01L21/76224 ,  H01L21/764 ,  H01L27/11524

摘要： A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

摘要翻译： 根据实施例的半导体存储器件包括半导体衬底上的有源区。 元件隔离布置在有源区之间并由绝缘膜填充。 配置为存储数据的多个存储单元形成在有效区域上。 在形成存储单元的有源区域的上端边缘部分和元件隔离中的绝缘膜之间布置有气隙。

公开(公告)号：US08624317B2

公开(公告)日：2014-01-07

申请号：US13402477

申请日：2012-02-22

申请人： Fumitaka Arai ,  Satoshi Nagashima ,  Hisataka Meguro ,  Hideto Takekida ,  Kenta Yamada

发明人： Fumitaka Arai ,  Satoshi Nagashima ,  Hisataka Meguro ,  Hideto Takekida ,  Kenta Yamada

IPC分类号： H01L29/792

CPC分类号： H01L27/11524 ,  G11C16/0466 ,  H01L27/11551 ,  H01L29/66825 ,  H01L29/7881

摘要： Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括第一存储单元阵列层，形成在其上的第一绝缘层和形成在其上的第二存储单元阵列层。 第一存储单元阵列层包括每个包括多个第一存储单元的第一NAND单元单元。 第一存储单元包括形成在其上的第一半导体层，第一栅极绝缘膜和在其上形成的第一电荷累积层。 第二存储单元阵列层包括每个包括多个第二存储单元的第二NAND单元单元。 第二存储单元包括第二电荷累积层，在其上形成的第二栅极绝缘膜，以及在其上形成的第二半导体层。 控制栅极经由栅极间绝缘膜，在第一和第二电荷累积层的第一方向两侧经由第一绝缘层位于前者之上。 控制门在垂直于第一方向的第二方向延伸。

公开(公告)号：US08466506B2

公开(公告)日：2013-06-18

申请号：US13053924

申请日：2011-03-22

申请人： Hideto Takekida

发明人： Hideto Takekida

IPC分类号： H01L29/788

CPC分类号： H01L27/11521

摘要： Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer.

摘要翻译： 非易失性半导体存储器件包括： 在第一虚拟细胞区域内的第一元件隔离绝缘层; 在第二虚拟单元区域内的第二元件隔离绝缘层; 以及在第一和第二虚拟单元区域之间的边界处的第三元件隔离绝缘层。 第一元件隔离绝缘层的顶表面位于比第一浮动电极层的顶表面更低的位置。 第二元件隔离绝缘层的顶表面位于与第二浮动电极层相同的高度。 第三元件隔离绝缘层具有顶表面。 邻接第一浮动电极层的顶表面的端部位于比第一浮动电极层的顶表面低的高度处。 第三元件隔离绝缘层的顶表面从第一浮动电极层的侧表面向第二浮动电极层的侧表面上升。

公开(公告)号：US08760935B2

公开(公告)日：2014-06-24

申请号：US13407991

申请日：2012-02-29

申请人： Hideto Takekida

发明人： Hideto Takekida

IPC分类号： G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/0483

摘要： A block dividing unit groups one-word lines into p groups, to divide a block into p divisional blocks. An erasing unit has an erasing operation performed on data stored in memory cells in a memory cell array, on a divisional block basis. An erasing verifying unit has an erasing verifying operation performed on memory cells subjected to the erasing operation, on a divisional block basis.

摘要翻译： 块分割单元将单字线组合成p组，以将块划分成p个划分块。 擦除单元对存储在存储单元阵列中的存储单元中的数据执行擦除操作，以划分块为基础。 擦除验证单元对按照划分块的擦除操作的存储器单元执行擦除验证操作。

公开(公告)号：US08427876B2

公开(公告)日：2013-04-23

申请号：US13188546

申请日：2011-07-22

申请人： Hideto Takekida

发明人： Hideto Takekida

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： In one embodiment, there is provided a semiconductor storage device including: a memory cell array; a high voltage generator; and a controller that controls the high voltage generator. When a word line to is selected from word lines, the controller controls the high voltage generator to: apply a first read pass voltage to one or two first adjacent word lines adjacent to the selected word line; apply a second read pass voltage to a second adjacent word line adjacent to the first adjacent word lines, wherein the second read pass voltage is higher than the first read pass voltage; and apply a third read pass voltage to remaining word lines other than the selected word line, the first adjacent word line and the second adjacent word line, wherein the third read pass voltage is higher than the first read pass voltage and lower than the second read pass voltage.

摘要翻译： 在一个实施例中，提供了一种半导体存储装置，包括：存储单元阵列; 高压发生器; 以及控制高电压发生器的控制器。 当从字线选择字线时，控制器控制高电压发生器：将第一读通过电压施加到与所选字线相邻的一个或两个第一相邻字线; 对与所述第一相邻字线相邻的第二相邻字线施加第二读取通过电压，其中所述第二读取通过电压高于所述第一读取通过电压; 对所选择的字线，所述第一相邻字线和所述第二相邻字线以外的剩余字线施加第三读取通过电压，其中所述第三读取通过电压高于所述第一读取通过电压且低于所述第二读取电流 通过电压。

公开(公告)号：US20090052242A1

公开(公告)日：2009-02-26

申请号：US12194655

申请日：2008-08-20

申请人： Hideto Takekida ,  Atsuhiro Sato ,  Fumitaka Arai

发明人： Hideto Takekida ,  Atsuhiro Sato ,  Fumitaka Arai

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A memory includes n-numbered memory cells (n is an integer of not less than 3) and a driver which applies a first voltage to a control gate electrode of a selected first memory cell in the n-numbered memory cells, applies a second voltage lower than the first voltage to a control gate electrode of a second memory cell adjacent to the first memory cell, and applies a third voltage lower than the second voltage to control gate electrodes of third memory cells other than the first and second memory cells at the time of programming. The first, second and third voltages have values not less than a value for turning on the n-numbered memory cells regardless of their threshold voltages.

摘要翻译： 存储器包括n编号的存储单元（n是不小于3的整数）和向第n个存储单元中的所选择的第一存储单元的控制栅电极施加第一电压的驱动器，施加第二电压 低于与第一存储单元相邻的第二存储单元的控制栅电极的第一电压，并施加比第二电压低的第三电压，以控制第一存储单元以外的第三存储单元的栅电极 编程时间。 第一，第二和第三电压具有不小于用于接通n个存储单元的值，不管其阈值电压如何。