公开(公告)号：US5572662A

公开(公告)日：1996-11-05

申请号：US455723

申请日：1995-05-31

申请人： Hidenobu Ohta ,  Tatsumi Nakada

发明人： Hidenobu Ohta ,  Tatsumi Nakada

IPC分类号： G06F11/18 ,  G06F11/16 ,  G06F15/16 ,  G06F15/177 ,  G06F11/34

CPC分类号： G06F11/1641 ,  G06F11/141 ,  G06F11/165

摘要： The invention provides a data processing apparatus wherein, when a trouble of a built-in RAM is detected, stopping of the system by a comparison check of the outputs of multiple CPUs is prevented and the trouble of the built-in RAM can be removed. The data processing apparatus includes a built-in RAM error detection section for detecting that an error occurs in a built-in RAM of any of processing sections, and an inhibition section for inhibiting, when the built-in RAM error detection section detects that a built-in RAM error occurs in at least one of the processing sections, the result of comparison outputted from the comparison section originating from the occurrence of the built-in RAM error. The data processing apparatus can be applied to various computer systems wherein multiple processing sections (CPUs) perform same operation and processing is performed while the outputs of the processing sections are compared with each other to confirm that the processing sections are performing same operation.

摘要翻译： 本发明提供一种数据处理装置，其中当检测到内置RAM的故障时，防止了通过对多个CPU的输出进行比较检查的系统的停止，并且可以消除内置RAM的故障。 数据处理装置包括：内置的RAM错误检测部，用于检测任何处理部的内置RAM中发生的错误;以及禁止部，其用于当内置RAM错误检测部检测到 在至少一个处理部分中发生内置RAM错误，从比较部分输出的比较结果源于内置RAM错误的发生。 数据处理装置可以应用于其中多个处理部分（CPU）执行相同的操作和处理的各种计算机系统，同时将处理部分的输出彼此进行比较，以确认处理部分正在执行相同的操作。

公开(公告)号：US07353440B2

公开(公告)日：2008-04-01

申请号：US10967280

申请日：2004-10-19

申请人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

发明人： Akihiko Ohwada ,  Tatsumi Nakada ,  Hitoshi Yamanaka

IPC分类号： G01R31/28

CPC分类号： G06F11/263 ,  G01R31/318547 ,  G06F11/267

摘要： In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.

摘要翻译： 在具有多个核的处理器（例如CMP）中，为每个逻辑块提供独立的MISR测试图案压缩电路，这使得可以更有效地执行LSI测试。 处理器包括多个逻辑块电路，其包括至少第一处理器核心电路和第二处理器核心电路，每个处理器核心电路具有扫描链电路并且可独立操作;以及公共块电路，具有扫描链电路 以及由第一处理器核心电路和第二处理器核心电路共享的高速缓存电路。 处理器还包括针对每个逻辑块的测试图形生成电路，其可操作以产生测试图案并将测试图案输入到每个逻辑块电路的扫描链，以及测试图案压缩电路，其可操作以接受作为输入并压缩 由每个逻辑块电路的扫描链输出的测试模式。

公开(公告)号：US06754813B1

公开(公告)日：2004-06-22

申请号：US09531608

申请日：2000-03-21

申请人： Tatsumi Nakada

发明人： Tatsumi Nakada

IPC分类号： G06F900

CPC分类号： G06F9/325 ,  G06F9/3846 ,  G06F9/3848

摘要： When a branch instruction for awaiting an event is detected in an information processing apparatus which performs a pipeline process including a branch prediction, a branch prediction for the branch instruction is suppressed. As a result, a prefetch operation for an instruction subsequent to the branch instruction is promoted, and the subsequent instruction is immediately executed when the event to be awaited occurs.

摘要翻译： 当在执行包括分支预测的流水线处理的信息处理装置中检测到用于等待事件的分支指令时，抑制了分支指令的分支预测。 结果，促进了分支指令之后的指令的预取操作，并且当待发生的事件发生时立即执行后续指令。

公开(公告)号：US5745533A

公开(公告)日：1998-04-28

申请号：US452539

申请日：1995-05-30

申请人： Yoshimi Asada ,  Tatsumi Nakada

发明人： Yoshimi Asada ,  Tatsumi Nakada

IPC分类号： G06F1/06 ,  G06F1/10 ,  H03K5/13 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0682 ,  G06F1/10

摘要： When a selector selects a first input terminal, a first loop circuit is formed including first and second input buffer circuits and an output buffer circuit. When the selector selects a second input terminal, a second loop circuit is formed including the first input buffer circuit and the output buffer circuit. When the selector selects a third input terminal, a third loop circuit is formed including the first input buffer circuit, a variable delay line (VDL), and the output buffer circuit. From the oscillating frequencies of loop circuits each formed as a ring oscillator, their respective signal delay times are obtained. By equalizing characteristics of first and second input buffer circuits, through a mutual operation using the signal delay times of respective loop circuits, a propagation delay time over a timing signal supply path including the first input buffer circuit and the VDL and stretching to a flip-flop is obtained precisely.

摘要翻译： 当选择器选择第一输入端时，形成包括第一和第二输入缓冲电路和输出缓冲电路的第一环路。 当选择器选择第二输入端时，形成包括第一输入缓冲电路和输出缓冲电路的第二环路。 当选择器选择第三输入端时，形成包括第一输入缓冲电路，可变延迟线（VDL）和输出缓冲电路的第三环路电路。 从环形振荡器形成的环路的振荡频率，得到各自的信号延迟时间。 通过均衡第一和第二输入缓冲电路的特性，通过使用各环路电路的信号延迟时间的相互操作，在包括第一输入缓冲电路和VDL的定时信号提供路径上的传播延迟时间， 翻牌是准确获得的。

公开(公告)号：US5634136A

公开(公告)日：1997-05-27

申请号：US569866

申请日：1995-12-08

申请人： Toshiharu Ohshima ,  Tatsumi Nakada

发明人： Toshiharu Ohshima ,  Tatsumi Nakada

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/40

CPC分类号： G06F9/30101 ,  G06F9/32 ,  G06F9/3804

摘要： There are provided a means for storing an instruction, a first control means for decoding and executing the instruction of said means for storing during a timing period which is used in said instruction, a means for computing an address data required for execution of said instruction, a first storage means having a plurality of registers for storing said computed address data, a means for selecting specific number resister in the first storage means, by controlling of the first control means during a timing period which is not used in said instruction, a second storage means for storing temporarily said address data in the specific number register selected by said means for selecting, a second control means for decoding the instruction before the first control means decoding and finding out the instruction to be branch instruction, and a means for outputting the address data from the second storage means as a target address data, when the register of the first storage means designated by said branch instruction coincides with the specific number register selected by the means for selecting.

摘要翻译： 提供了一种用于存储指令的装置，用于解码和执行在所述指令中使用的定时周期期间存储的所述装置的指令的第一控制装置，用于计算执行所述指令所需的地址数据的装置， 第一存储装置，具有用于存储所述计算的地址数据的多个寄存器，用于通过在所述指令中不使用的定时周期期间控制第一控制装置来选择第一存储装置中的特定号码寄存器的装置，第二存储装置 存储装置，用于临时存储由所述用于选择的装置选择的特定号码寄存器中的所述地址数据;第二控制装置，用于对第一控制装置解码之前的指令进行解码，并找出作为分支指令的指令;以及装置， 当第一存储装置的寄存器被指定时，来自第二存储装置的地址数据作为目标地址数据 通过所述分支指令与由所述选择装置选择的特定号码寄存器一致。

公开(公告)号：US20050144409A1

公开(公告)日：2005-06-30

申请号：US11059472

申请日：2005-02-16

申请人： Akira Nodomi ,  Tatsumi Nakada ,  Eiki Ito ,  Hideki Sakata

发明人： Akira Nodomi ,  Tatsumi Nakada ,  Eiki Ito ,  Hideki Sakata

IPC分类号： G06F12/00 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： Each of a plurality of memory blocks returns data in different latency in reply to a data request from a request source. The closer a request destination memory block is to the request source, in the shorter latency the data is returned.

摘要翻译： 多个存储块中的每一个响应于来自请求源的数据请求而以不同的等待时间返回数据。 请求目的地内存块越接近请求源，数据返回的延迟越短。

公开(公告)号：US20050102473A1

公开(公告)日：2005-05-12

申请号：US11009466

申请日：2004-12-13

申请人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

发明人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1054 ,  G06F12/1063

摘要： A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

摘要翻译： 高速缓存控制方法控制具有包含关系的多级高速缓存的处理器系统中的数据共享条件。 高速缓存控制方法通过实际地址对上级高速缓存进行索引，并通过虚拟地址对较低级别的高速缓存进行索引，并且防止多个不同的虚拟地址引用的实际地址在同一高速缓存中多次登记 。 多个虚拟地址可注册在高级缓存内，以便放松数据共享条件。

公开(公告)号：US5781433A

公开(公告)日：1998-07-14

申请号：US406075

申请日：1995-03-17

申请人： Kenichi Nabeya ,  Tatsumi Nakada

发明人： Kenichi Nabeya ,  Tatsumi Nakada

IPC分类号： G06F11/16 ,  G06F9/38 ,  G06F11/00 ,  G05B9/02

CPC分类号： G06F9/3885 ,  G06F11/00 ,  G06F9/3838 ,  G06F9/3861

摘要： In a computer system having a coprocessor dedicated to arithmetic operations, one of the coprocessor and CPU is equipped with an abnormality decision section and the other is equipped with a transmission section which transmits to the abnormality decision section signals by which the abnormality decision section is permitted to decide whether abnormality has occurred. In a first arrangement, upon detecting that an instruction transferred from the CPU is abnormal, the coprocessor turns off a flag indicating that it is active. In the CPU, its internal storage state indicates that the coprocessor is active and the flag is received which indicates that the coprocessor is inactive. Thereby, the CPU is permitted to decide that abnormality has occurred. In a second arrangement, upon detecting abnormality, the coprocessor turns off that flag indicating that it is active and turns on a flag indicating that the buffer is full. By receiving this signal state which cannot usually exist, the CPU is permitted to decide that abnormality has occurred.

摘要翻译： 在具有专用于算术运算的协处理器的计算机系统中，协处理器和CPU中的一个配备有异常判定部，另一个配备有发送部，其向异常判定部发送允许异常判定部的信号 决定是否发生异常。 在第一布置中，当检测到从CPU传送的指令异常时，协处理器关闭指示其处于活动状态的标志。 在CPU中，其内部存储状态表示协处理器处于活动状态，并且接收到指示协处理器处于非活动状态的标志。 由此，CPU被允许判定发生异常。 在第二种配置中，当检测到异常时，协处理器关闭指示它是活动的标志，并且打开指示缓冲器已满的标志。 通过接收通常不存在的该信号状态，CPU被允许判定发生异常。

公开(公告)号：US5638526A

公开(公告)日：1997-06-10

申请号：US364512

申请日：1994-12-27

申请人： Tatsumi Nakada

发明人： Tatsumi Nakada

IPC分类号： G06F9/34 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30141 ,  G06F9/3824

摘要： A register read control method for use with an information processing apparatus for executing a plurality of instructions in parallel during pipeline processing. The apparatus includes a register file, a register designation selector, a cache register, a selector, an arithmetic circuit, a register cache pass and a comparator. When the comparator detects a coincidence between the data in the cache register for the current instruction and the operand in the next instruction, the comparator causes the selector to select the register cache pass as input thereto and to move the contents of the cache register back directly to the cache register via the register cache pass.

摘要翻译： 一种用于在流水线处理期间并行执行多个指令的信息处理装置的寄存器读取控制方法。 该装置包括寄存器文件，寄存器指定选择器，高速缓存寄存器，选择器，运算电路，寄存器高速缓存通路和比较器。 当比较器检测到当前指令的高速缓存寄存器中的数据与下一条指令中的操作数之间的一致时，比较器使选择器选择寄存器高速缓存通过作为其输入，并将缓存寄存器的内容直接返回 通过寄存器缓存通过到缓存寄存器。

公开(公告)号：US07330961B2

公开(公告)日：2008-02-12

申请号：US11009466

申请日：2004-12-13

申请人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

发明人： Hideki Sakata ,  Tatsumi Nakada ,  Eiki Ito ,  Akira Nodomi

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1054 ,  G06F12/1063

摘要： A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.

摘要翻译： 高速缓存控制方法控制具有包含关系的多级高速缓存的处理器系统中的数据共享条件。 高速缓存控制方法通过实际地址对上级高速缓存进行索引，并通过虚拟地址对较低级别的高速缓存进行索引，并且防止多个不同的虚拟地址引用的实际地址在同一高速缓存中多次登记 。 多个虚拟地址可注册在高级缓存内，以便放松数据共享条件。