公开(公告)号：US20060258115A1

公开(公告)日：2006-11-16

申请号：US11405539

申请日：2006-04-18

申请人： Takahito Nakajima ,  Masahito Shinohe

发明人： Takahito Nakajima ,  Masahito Shinohe

IPC分类号： H01L21/76

CPC分类号： H01L27/1087

摘要： A method of manufacturing a semiconductor device includes forming a trench in a semiconductor substrate, forming a film containing impurities on an inner surface of a lower part of the trench, forming a silicon nitride film so that an upper sidewall of the trench is covered by the silicon nitride film, and diffusing the impurities outside the trench by heat treatment.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽的下部的内表面上形成含有杂质的膜，形成氮化硅膜，使得沟槽的上侧壁被 氮化硅膜，并通过热处理将杂质扩散到沟槽外。

公开(公告)号：US07485909B2

公开(公告)日：2009-02-03

申请号：US11433465

申请日：2006-05-15

申请人： Takanori Matsumoto ,  Masahito Shinohe

发明人： Takanori Matsumoto ,  Masahito Shinohe

IPC分类号： H01L31/112 ,  H01L29/12 ,  H01L27/108 ,  H01L21/338 ,  H01L21/337 ,  H01L21/8238 ,  H01L21/8249 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/94

摘要： A semiconductor device includes a semiconductor substrate formed with a trench having a sidewall including a middle point. The trench includes a first part extending from a surface of the semiconductor substrate to the middle point of the trench and having a diameter that is gradually reduced as the first part extends deeper from the surface of the semiconductor substrate to the middle point of the trench. The trench includes a second part that is deeper than the middle point of the sidewall and that has a larger diameter than the middle point of the sidewall. An electrically conductive film is formed in an interior of the trench so as to be located lower than the middle point of the sidewall, the conductive film having a planarized upper surface, and a collar insulating film is formed on the conductive film and the sidewall of the trench so as to extend through the middle point of the sidewall along the sidewall.

摘要翻译： 半导体器件包括形成有沟槽的半导体衬底，该沟槽具有包括中间点的侧壁。 沟槽包括从半导体衬底的表面延伸到沟槽的中点的第一部分，并且具有随着第一部分从半导体衬底的表面更深地延伸到沟槽的中点而逐渐减小的直径。 沟槽包括比侧壁的中点更深的并且具有比侧壁的中点更大的直径的第二部分。 导电膜形成在沟槽的内部，以便位于比侧壁的中点更低的位置，导电膜具有平坦化的上表面，并且在导电膜和侧壁上形成轴环绝缘膜 沟槽，以便沿着侧壁延伸穿过侧壁的中点。

公开(公告)号：US20070085125A1

公开(公告)日：2007-04-19

申请号：US11638492

申请日：2006-12-14

申请人： Hirofumi Inoue ,  Masahito Shinohe

发明人： Hirofumi Inoue ,  Masahito Shinohe

IPC分类号： H01L29/94

CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10867

摘要： A trench capacitor is formed in a semiconductor substrate with a capacitor insulating film. The trench has a conductive layer as storage node electrode buried in a trench. The conductive layer includes a first, a second, and third conductive layer. The first conductive layer is buried in a lower portion of the trench. The second conductive layer is buried in a recess on the upper surface of the first conductive layer. The third conductive layer is buried to contact with the first and second conductive layers.

摘要翻译： 在具有电容器绝缘膜的半导体衬底中形成沟槽电容器。 沟槽具有作为存储节点电极的导电层，埋入沟槽中。 导电层包括第一，第二和第三导电层。 第一导电层被埋在沟槽的下部。 第二导电层被埋在第一导电层的上表面上的凹部中。 掩埋第三导电层以与第一和第二导电层接触。

公开(公告)号：US07525142B2

公开(公告)日：2009-04-28

申请号：US11638492

申请日：2006-12-14

申请人： Hirofumi Inoue ,  Masahito Shinohe

发明人： Hirofumi Inoue ,  Masahito Shinohe

IPC分类号： H01L27/108

CPC分类号： H01L21/76877 ,  H01L21/76849 ,  H01L27/10867

摘要： A trench capacitor is formed in a semiconductor substrate with a capacitor insulating film. The trench has a conductive layer as storage node electrode buried in a trench. The conductive layer includes a first, a second, and third conductive layer. The first conductive layer is buried in a lower portion of the trench. The second conductive layer is buried in a recess on the upper surface of the first conductive layer. The third conductive layer is buried to contact with the first and second conductive layers.

摘要翻译： 在具有电容器绝缘膜的半导体衬底中形成沟槽电容器。 沟槽具有作为存储节点电极的导电层，埋入沟槽中。 导电层包括第一，第二和第三导电层。 第一导电层被埋在沟槽的下部。 第二导电层被埋在第一导电层的上表面上的凹部中。 掩埋第三导电层以与第一和第二导电层接触。

公开(公告)号：US07923371B2

公开(公告)日：2011-04-12

申请号：US12405482

申请日：2009-03-17

申请人： Masahito Shinohe

发明人： Masahito Shinohe

IPC分类号： H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L27/11519 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the semiconductor substrate in a zigzag pattern in a second direction perpendicular to the first direction, wherein the contact plugs have a rectangular cross section.

摘要翻译： 半导体器件具有半导体衬底，其中多个器件区域和多个器件隔离区域交替地形成为沿第一方向延伸; 以及形成在所述半导体基板上的多个接触插塞，其与所述器件区域连接，并且在与所述第一方向垂直的第二方向上以锯齿形图案布置在所述半导体衬底上，其中所述接触插塞具有矩形横截面。

公开(公告)号：US20060255390A1

公开(公告)日：2006-11-16

申请号：US11433465

申请日：2006-05-15

申请人： Takanori Matsumoto ,  Masahito Shinohe

发明人： Takanori Matsumoto ,  Masahito Shinohe

IPC分类号： H01L29/00 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/94

摘要： A semiconductor device includes a semiconductor substrate formed with a trench having a bottleneck and a sidewall, an electrically conductive film formed in an interior of the trench so as to be located lower than the bottleneck, the conductive film having a planarized upper surface, and a collar insulating film formed on the conductive film and the sidewall of the trench so as to extend through the bottleneck along the sidewall.

摘要翻译： 半导体器件包括形成有具有瓶颈和侧壁的沟槽的半导体衬底，形成在沟槽内部以便位于低于瓶颈的导电膜，导电膜具有平坦化的上表面，以及 形成在导电膜和沟槽的侧壁上的环形绝缘膜，以沿着侧壁延伸穿过瓶颈。

公开(公告)号：US20120241836A1

公开(公告)日：2012-09-27

申请号：US13338723

申请日：2011-12-28

申请人： Nobuhito KUGE ,  Masahito Shinohe

发明人： Nobuhito KUGE ,  Masahito Shinohe

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L27/11524 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： According to one embodiment, a method of manufacturing a semiconductor device including a memory cell transistor in a first region of a substrate and a select gate transistor in a second region of the substrate includes: forming a gate insulating film, a lower gate electrode, an inter-electrode insulating film, an upper gate electrode, and a hard mask on the substrate; forming a groove passing through the hard mask, the upper gate electrode, and the inter-electrode insulating film and reaching the lower gate electrode in the second region; and forming a connection layer having a crystal structure which preferentially has a specific crystal orientation and that electrically connects between the lower gate electrode and the upper gate electrode by being selectively crystal-grown while being subjected to an influence from a crystal structure of the lower gate electrode in the groove

摘要翻译： 根据一个实施例，一种制造半导体器件的方法，包括在衬底的第一区域中的存储单元晶体管和衬底的第二区域中的选择栅极晶体管，包括：形成栅极绝缘膜，下部栅电极， 基板上的电极间绝缘膜，上栅电极和硬掩模; 在所述第二区域中形成穿过所述硬掩模，所述上栅电极和所述电极间绝缘膜并到达所述下栅电极的沟槽; 并且形成具有优选具有特定晶体取向的晶体结构的连接层，并且通过选择性地晶体生长同时受到下栅极的晶体结构的影响而电连接在下栅电极和上栅电极之间 电极在槽中