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7 条记录 (耗时 0.018 秒)

    Semi-custom integrated circuit device
    3.
    发明授权
    Semi-custom integrated circuit device 失效
    半定制集成电路器件

    公开(公告)号：US5281835A

    公开(公告)日：1994-01-25

    申请号：US825733

    申请日：1992-01-27

    申请人： Masayoshi Tomita ,  Tadahiro Saitoh ,  Kiyokazu Hasegawa ,  Noboru Kosugi

    发明人： Masayoshi Tomita ,  Tadahiro Saitoh ,  Kiyokazu Hasegawa ,  Noboru Kosugi

    IPC分类号： H01L27/118 ,  H01L29/78 ,  H01L27/10

    CPC分类号： H01L27/11807 ,  H01L27/118

    摘要： A semi-custom integrated circuit comprises a basic cell array comprising a plurality of basic cells aligned in a first direction, the basic cells comprising a transistor unit, a capacitor unit and a resistor unit arranged in a second direction perpendicular to the first direction. The transistor unit is positioned between the capacitor unit and the resistor unit. The transistor unit has a terminal portion for connection of wiring, the capacitor unit having a terminal portion for connection of wiring, the resistor unit having a terminal portion for connection of wiring. The terminal portions of said transistor unit, capacitor unit and resistor unit are aligned along a line.

    摘要翻译： 半定制集成电路包括基本单元阵列，其包括沿第一方向对准的多个基本单元，所述基本单元包括在垂直于第一方向的第二方向上布置的晶体管单元，电容器单元和电阻器单元。 晶体管单元位于电容器单元和电阻单元之间。 晶体管单元具有用于连接布线的端子部分，电容器单元具有用于连接布线的端子部分，该电阻器单元具有用于连接布线的端子部分。 所述晶体管单元，电容器单元和电阻器单元的端子部分沿着一条直线排列。

    Semiconductor device having embedded array
    5.
    发明授权
    Semiconductor device having embedded array 失效
    具有嵌入式阵列的半导体器件

    公开(公告)号：US06886142B2

    公开(公告)日：2005-04-26

    申请号：US10067881

    申请日：2002-02-08

    申请人： Noboru Yokota ,  Hisayoshi Oba ,  Noboru Kosugi ,  Munehiro Tahara

    发明人： Noboru Yokota ,  Hisayoshi Oba ,  Noboru Kosugi ,  Munehiro Tahara

    IPC分类号： H01L21/8234 ,  G01R31/28 ,  H01L21/66 ,  H01L21/76 ,  H01L21/82 ,  H01L23/544 ,  H01L27/088 ,  H01L27/118 ,  G06F17/50

    CPC分类号： G01R31/2884 ,  H01L22/20 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

    摘要翻译： 设计并制造具有嵌入阵列的半导体集成电路，其中基本单元被布置成矩阵（S1）; 对半导体集成电路的原型的电气性能是否满足要求的规格进行测试（S 2）; 如果满足，则基于接触孔的布局数据检测并去除嵌入阵列区域中的非使用区域模式以获得修改的模式（S 4）; 制备具有改良图案的掩模（S 5）; 并且在修改之前将掩模代替掩模，从而制造除去非使用区域的半导体集成电路（S 6）。

    Load cell
    7.
    发明授权
    Load cell 失效
    称重传感器

    公开(公告)号：US5052505A

    公开(公告)日：1991-10-01

    申请号：US528580

    申请日：1990-05-24

    申请人： Kazufumi Naito ,  Seiji Nishide ,  Hiroyuki Konishi ,  Noboru Kosugi

    发明人： Kazufumi Naito ,  Seiji Nishide ,  Hiroyuki Konishi ,  Noboru Kosugi

    IPC分类号： G01G3/14 ,  G01L1/22

    CPC分类号： G01L1/2243 ,  G01G3/1412 ,  G01L1/2287

    摘要： A load cell has a cantilever-type load-sensitive element with an upper beam and a lower beam, each having formed thereon a pair of strain-generating parts which generates a strain corresponding to an applied load. Only one of these two beams has an indented part formed on its surface and strain-detecting elements are attached to its bottom surface at positions corresponding to the strain-generating parts. A moisture-proof sheet is attached to the beam to completely seal the interior of this indented part to protect the strain-detecting elements from humidity and moisture.