公开(公告)号：US07800227B2

公开(公告)日：2010-09-21

申请号：US11240645

申请日：2005-10-03

申请人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

发明人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

IPC分类号： H01L23/522

CPC分类号： H01L24/05 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/48

摘要： In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

摘要翻译： 在包括多层衬垫的半导体器件中，多层衬垫包括设置在半导体衬底上的第一衬底层，其具有设置在第一铜布线区域内的第一铜布线区域和第一层间绝缘区域，以及设置在第一铜布线区域上的第二衬垫层 所述第一焊盘层经由层间绝缘膜，以具有设置在所述第二铜布线区域内的第二铜布线区域和第二层间绝缘区域。 在半导体装置中，第一铜布线区域，第一内层绝缘区域，第二铜布线区域和第二层间绝缘区域设置在第一和第二焊盘层中，使得多层焊盘具有布局，其中， 当从半导体衬底的垂直上方观察多层衬垫时，用铜布线覆盖区域。

公开(公告)号：US6013924A

公开(公告)日：2000-01-11

申请号：US880443

申请日：1997-06-23

申请人： Toru Osajima ,  Noboru Yokota ,  Takashi Iida ,  Masashi Takase ,  Shigenori Ichinose

发明人： Toru Osajima ,  Noboru Yokota ,  Takashi Iida ,  Masashi Takase ,  Shigenori Ichinose

IPC分类号： H01L21/82 ,  H01L27/118

CPC分类号： H01L27/118 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14

摘要： A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.

摘要翻译： 半导体集成电路包括半导体芯片; 内细胞区; 位于内单元区域周围的多个输入/输出单元区域以及设置在半导体芯片的多个输入/输出区域和侧面之间的多个焊盘。 将多个输入/输出单元区域中的每个单位区域分配给相应的输入/输出单元，以便对于相应的输入/输出单元来说足够。

公开(公告)号：US20060097396A1

公开(公告)日：2006-05-11

申请号：US11240645

申请日：2005-10-03

申请人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

发明人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/48

摘要： In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

摘要翻译： 在包括多层衬垫的半导体器件中，多层衬垫包括设置在半导体衬底上的第一衬底层，其具有设置在第一铜布线区域内的第一铜布线区域和第一层间绝缘区域，以及设置在第一铜布线区域上的第二衬垫层 所述第一焊盘层经由层间绝缘膜，以具有设置在所述第二铜布线区域内的第二铜布线区域和第二层间绝缘区域。 在半导体装置中，在第一和第二焊盘层中设置第一铜布线区域，第一层内绝缘区域，第二铜布线区域和第二层间绝缘区域，使得多层焊盘具有布局，其中， 当从半导体衬底的垂直上方观察多层衬垫时，用铜布线覆盖区域。

公开(公告)号：US20060022691A1

公开(公告)日：2006-02-02

申请号：US11242082

申请日：2005-10-04

申请人： Takanori Watanabe ,  Masashi Takase ,  Noboru Kosugi

发明人： Takanori Watanabe ,  Masashi Takase ,  Noboru Kosugi

IPC分类号： G01R31/02

CPC分类号： G01R31/2884 ,  H01L22/32 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074

摘要： It is able to restrict increase of a chip area even if the pad pitch is reduced and the pad length is increased in a semiconductor device by arranging pads (4, 5), comprising electrically connected first and second regions having different number of wiring layers, above an I/O circuit (2).

摘要翻译： 即使通过布置包括具有不同数量的布线层的电连接的第一和第二区域的焊盘（4,5），即使焊盘间距减小并且半导体器件中的焊盘长度增加，也能够限制芯片面积的增加， 在I / O电路（2）之上。