公开(公告)号：US07970998B2

公开(公告)日：2011-06-28

申请号：US11910831

申请日：2006-03-17

申请人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

发明人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F12/0848 ,  G06F12/0888

摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。

公开(公告)号：US20090077318A1

公开(公告)日：2009-03-19

申请号：US11910831

申请日：2006-03-17

申请人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

发明人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0875 ,  G06F12/0848 ,  G06F12/0888

摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。

公开(公告)号：US20090100231A1

公开(公告)日：2009-04-16

申请号：US11816858

申请日：2006-02-08

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

IPC分类号： G06F12/08

CPC分类号： G06F12/12 ,  G06F12/0802 ,  G06F12/0893

摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。

公开(公告)号：US07953935B2

公开(公告)日：2011-05-31

申请号：US11816858

申请日：2006-02-08

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko

IPC分类号： G06F13/00

CPC分类号： G06F12/12 ,  G06F12/0802 ,  G06F12/0893

摘要： A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

摘要翻译： 容易接受用于处理的软件控制的高速缓冲存储器系统包括：设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC（传送和属性控制器）。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标，以便请求针对该地址的命令所指示的操作 高速缓存存储器。

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。

公开(公告)号：US20090094474A1

公开(公告)日：2009-04-09

申请号：US11994041

申请日：2005-12-26

申请人： Keisuke Kaneko ,  Masaitsu Nakajima ,  Takanobu Tani

发明人： Keisuke Kaneko ,  Masaitsu Nakajima ,  Takanobu Tani

IPC分类号： G06F12/02 ,  G06F1/04

CPC分类号： G06F9/383 ,  G06F9/345 ,  G06F9/3832 ,  G06F9/3875

摘要： An information processing device controls an access unit which accesses a memory corresponding to an address space where an address belongs, the address being generated using at least two pieces of address generation source information. The information processing device includes: a prediction unit which predicts one or more address spaces where the address to be accessed may potentially belong, using one piece of the address generation source information; an activation unit which activates accesses from the access unit to memories corresponding to all the address spaces predicted by the prediction unit; a determination unit which determines the address space where the address to be accessed belongs, the address being generated using the at least two pieces of the address generation source information; and an access stop unit which stops the accesses from the access unit, except for the access corresponding to the address space determined by the determination unit, out of the accesses activated under control of the activation unit.

摘要翻译： 信息处理装置控制访问与地址所属的地址空间对应的存储器的访问单元，使用至少两个地址生成源信息生成地址。 信息处理装置包括：使用一段地址生成源信息来预测要访问的地址可能属于的一个或多个地址空间的预测单元; 激活单元，其激活从所述访问单元访问对应于由所述预测单元预测的所有地址空间的存储器; 确定要访问的地址所在的地址空间的确定单元，使用所述至少两个地址生成源信息生成的地址; 以及访问停止单元，除了在由激活单元的控制下激活的访问之外，停止对由所述确定单元确定的地址空间相对应的访问以外的访问单元的访问。

公开(公告)号：US07000135B2

公开(公告)日：2006-02-14

申请号：US10093543

申请日：2002-03-08

申请人： Keisuke Kaneko

发明人： Keisuke Kaneko

IPC分类号： G06F1/12 ,  G06F9/30 ,  G06F15/00

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

摘要： In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to the processing circuit, the number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing is extracted, the extracted number of cycles is transferred to the clock supply control circuit, the supply of the clock is started when the processing is started in the processing circuit, and the supply of the clock to the processing circuit is stopped when the supply of the clock with the number of cycles is completed. Thus, a clock control method and an information processing device employing the clock control method are provided that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing.

公开(公告)号：US6161171A

公开(公告)日：2000-12-12

申请号：US105212

申请日：1998-06-26

申请人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

发明人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3867 ,  G06F12/0855

摘要： A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

摘要翻译： 需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令，然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令 设置，应加入管道处理。 在提供具有较高频率的操作时钟的高速模式中，控制指令执行电路和数据存储器之间的数据高速缓冲存储器，以将数据字提供给指令执行的WB（回写）级 电路相对于与第一指令相关联的输入地址在两个周期内。 为了执行第二指令，数据字从WB级提供给指令执行电路的EX（操作执行）级。 在提供具有较低频率的操作时钟的低速模式中，控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM（存储器访问）级 与第一条指令相关联。 为了执行第二条指令，将数据字从MEM级旁路到EX级。

公开(公告)号：US20130316256A1

公开(公告)日：2013-11-28

申请号：US13997807

申请日：2011-12-27

申请人： Keisuke Kaneko ,  Takeshi Ibuka

发明人： Keisuke Kaneko ,  Takeshi Ibuka

IPC分类号： H01M8/04

CPC分类号： H01M8/0444 ,  H01M8/04335 ,  H01M8/04373 ,  H01M8/04395 ,  H01M8/04447 ,  H01M8/04462 ,  H01M8/04738 ,  H01M8/04753 ,  H01M8/04835 ,  H01M8/0491 ,  H01M8/0612

摘要： This fuel cell system monitors the temperature of an off-gas combusting unit detected by a combustor temperature detecting unit in a constant output operation state such as a rated operation state where a sweeping current of a cell stack becomes constant, rather than directly measuring the fuel property, and controls the flow rate of the cathode gas so that the temperature of the off-gas combusting unit reaches a target temperature. Moreover, the fuel cell system determines the fuel property based on the variation of the flow rate of the cathode gas changed until the temperature of the off-gas combusting unit reaches the target temperature and the temperature of the cathode gas. Thus, it is possible to simplify the configuration required for determining whether the fuel property has changed or not as compared to a conventional method of measuring a plurality of factors of the fuel property.

摘要翻译： 该燃料电池系统以恒定的输出运行状态监视由燃烧器温度检测部检测出的废气燃烧部的温度，例如电池堆的扫掠电流恒定的额定运行状态，而不是直接测量燃料 性能，并控制阴极气体的流量，使得废气燃烧单元的温度达到目标温度。 此外，燃料电池系统基于改变的阴极气体的流量的变化来确定燃料特性，直到废气燃烧单元的温度达到目标温度和阴极气体的温度。 因此，与传统的测量燃料特性因素的方法相比，可以简化确定燃料特性是否变化所需的结构。

公开(公告)号：US07636812B2

公开(公告)日：2009-12-22

申请号：US11720751

申请日：2006-03-22

申请人： Keisuke Kaneko

发明人： Keisuke Kaneko

IPC分类号： G06F13/14

CPC分类号： G06F12/0864 ,  G06F12/084 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).

摘要翻译： 本发明的目的是降低伴随高速缓存命中/错误确定的功耗。 为了实现该目的，当访问具有用于设置是否允许针对每个CPU或每个线程的高速缓冲存储器中的每个路径的高速缓存重新填充的装置的缓存存储器时，首先，仅在 设置补充的方式（步骤2-1和2-2），并且如果第一高速缓存命中/未命中确定导致高速缓存命中，则访问结束（步骤2-6）。 在缓存未命中的情况下，访问不设置允许的方式（步骤2-3），或者通过访问所有方式执行第二命中/未命中确定（步骤2-4）。