公开(公告)号：US07970998B2

公开(公告)日：2011-06-28

申请号：US11910831

申请日：2006-03-17

申请人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

发明人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

IPC分类号： G06F12/08

CPC分类号： G06F12/0875 ,  G06F12/0848 ,  G06F12/0888

摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。

公开(公告)号：US20090077318A1

公开(公告)日：2009-03-19

申请号：US11910831

申请日：2006-03-17

申请人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

发明人： Takao Yamamoto ,  Tetsuya Tanaka ,  Ryuta Nakanishi ,  Masaitsu Nakajima ,  Keisuke Kaneko ,  Hazuki Okabayashi

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0875 ,  G06F12/0848 ,  G06F12/0888

摘要： A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

摘要翻译： 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器，当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时，判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断，以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元，并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。

公开(公告)号：US07502887B2

公开(公告)日：2009-03-10

申请号：US10578314

申请日：2004-09-08

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Takao Yamamoto ,  Keisuke Kaneko

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/121 ,  G06F12/126

摘要： The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

摘要翻译： 本发明中的高速缓存存储器是N路组相关高速缓冲存储器，其包括表示N路中的一种或多种方式的控制寄存器，激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。

公开(公告)号：US20100174884A1

公开(公告)日：2010-07-08

申请号：US12159271

申请日：2006-11-09

申请人： Hiroyuki Morishita ,  Takao Yamamoto ,  Masaitsu Nakajima

发明人： Hiroyuki Morishita ,  Takao Yamamoto ,  Masaitsu Nakajima

IPC分类号： G06F9/302 ,  G06F9/30 ,  G06F15/80 ,  G06F9/06

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30181 ,  G06F9/3897

摘要： A processor (101) in which a plurality of arithmetic elements executing instructions are embedded includes: fixed function arithmetic elements (121 to 123) each having a circuit configuration that is not dynamically reconfigurable; a reconfigurable arithmetic element (125) having a circuit configuration that is dynamically reconfigurable; and an arithmetic operation control unit (113) which allocates instructions to the fixed function arithmetic elements (121 to 123) and the reconfigurable arithmetic element (125) and issues the allocated instructions to the respective arithmetic elements.

摘要翻译： 其中嵌入执行指令的多个运算元件的处理器（101）包括：每个具有不能动态重新配置的电路配置的固定功能运算元件（121至123） 具有可动态重新配置的电路配置的可重构算术元件（125）; 以及向所述固定功能运算元件（121〜123）和所述可重构运算元件（125）分配指令的运算控制单元（113），并且将分配的指令发布给各个运算元件。

公开(公告)号：US20070088896A1

公开(公告)日：2007-04-19

申请号：US11510670

申请日：2006-08-28

申请人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

发明人： Masahide Kakeda ,  Masaitsu Nakajima ,  Takao Yamamoto ,  Shinji Ozaki

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0893 ,  G06F12/0831

摘要： A cache access transmission means outputs an access address, obtained from a CPU by way of a local cache access address input means, to a shared address bus via a remote cache access address output means. A cache access control means accesses a cache memory by using the access address obtained from the shared address bus by way of a remote cache access address input means. That is, an access address output from a CPU of a first processor is output from the cache access transmission means and received by the cache access control means so as to be used in accessing a cache memory in a second processor.

摘要翻译： 高速缓存存取传输装置经由远程高速缓存存取地址输出装置将通过本地高速缓存存取地址输入装置从CPU获得的访问地址输出到共享地址总线。 高速缓存访​​问控制装置通过使用通过远程高速缓存访​​问地址输入装置从共享地址总线获得的访问地址来访问高速缓冲存储器。 也就是说，从高速缓存访​​问传输装置输出从第一处理器的CPU输出的访问地址，并由高速缓存访​​问控制装置接收，以便用于访问第二处理器中的高速缓冲存储器。

公开(公告)号：US08850168B2

公开(公告)日：2014-09-30

申请号：US13215623

申请日：2011-08-23

申请人： Takao Yamamoto ,  Shinji Ozaki ,  Masahide Kakeda ,  Masaitsu Nakajima

发明人： Takao Yamamoto ,  Shinji Ozaki ,  Masahide Kakeda ,  Masaitsu Nakajima

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F9/462 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.

摘要翻译： 根据本发明的处理器装置是在多个处理器之间共享硬件资源的处理器装置，包括：第一确定单元，确定每个硬件资源中的寄存器是否保存有程序的扩展上下文数据， 目前执行; 第二确定单元，确定硬件资源中的扩展上下文数据对哪个处理器; 第一传送单元，其在所述处理器中的节目之间保存和恢复所述扩展上下文数据; 以及第二传送单元，其在不同处理器之间的节目之间保存和恢复扩展上下文数据。

公开(公告)号：US08141088B2

公开(公告)日：2012-03-20

申请号：US11936296

申请日：2007-11-07

申请人： Hiroyuki Morishita ,  Shinji Ozaki ,  Takao Yamamoto ,  Masaitsu Nakajima

发明人： Hiroyuki Morishita ,  Shinji Ozaki ,  Takao Yamamoto ,  Masaitsu Nakajima

IPC分类号： G06F9/46 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3851

摘要： Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.

摘要翻译： 提供了一种可以准确地估计每个线程所需的处理时间的多线程处理器，以及同时执行指令流的多线程处理器，所述多线程处理器包括：执行指令的计算单元组; 指令调度器，其将指令分组为每个指令流，每个指令流中包括指令，并且每个组由指令同时发出到计算单元; 指令缓冲器，其保存由指令调度器分组的每个组的指令，所述指令被包括在每个指令流中; 以及发出指令确定单元，其在多线程处理器的每个执行周期中从指令缓冲器读取每个组的指令，并将读取指令发布到计算单元组。

公开(公告)号：US06385720B1

公开(公告)日：2002-05-07

申请号：US09114274

申请日：1998-07-13

申请人： Tetsuya Tanaka ,  Takao Yamamoto

发明人： Tetsuya Tanaka ,  Takao Yamamoto

IPC分类号： G06F1500

CPC分类号： G06F9/382 ,  G06F9/325 ,  G06F9/3844

摘要： In branch prediction in accordance with the present invention, in order to reduce the storage capacity for storing branch prediction information and simplify an information retrieval circuit while minimizing reduction in branch prediction accuracy, the position of an instruction is stored in advance and an instruction is decoded for execution, the relative position of the instruction decoded for execution is obtained on the basis of the position of the stored instruction, and when the decoded instruction is a branch instruction the result of branch by the branch instruction is recorded as history information in correspondence with the relative position of the branch instruction. After this, an instruction is pre-decoded before execution, the relative position of the pre-decoded instruction is obtained on the basis of the position of the stored instruction, when the pre-decoded instruction is a branch instruction the history information corresponding to the relative position of the pre-decoded branch instruction is referred to, and the result of the execution of the pre-decoded branch instruction is predicted by using the result of the reference to the history information.

摘要翻译： 在根据本发明的分支预测中，为了减小用于存储分支预测信息的存储容量并简化信息检索电路，同时最小化分支预测精度的降低，指令的位置被预先存储并且指令被解码 为了执行，基于存储指令的位置获得执行解码指令的相对位置，并且当解码指令是分支指令时，分支指令的分支结果被记录为对应于 分支指令的相对位置。 之后，在执行前对指令进行预解码，当预解码指令是分支指令时，基于存储指令的位置获得预解码指令的相对位置，对应于 参考预解码分支指令的相对位置，并且通过使用对历史信息的引用的结果来预测执行预解码分支指令的结果。

公开(公告)号：US08702509B2

公开(公告)日：2014-04-22

申请号：US13634500

申请日：2011-03-11

申请人： Takao Yamamoto

发明人： Takao Yamamoto

IPC分类号： A63F13/00

CPC分类号： A63F13/44 ,  A63F13/2145 ,  A63F13/426 ,  A63F13/46 ,  A63F13/5375 ,  A63F13/54 ,  A63F13/814 ,  A63F2300/1075 ,  A63F2300/305 ,  A63F2300/6045 ,  A63F2300/61 ,  A63F2300/638 ,  A63F2300/8047

摘要： Disclosed is a game system comprising a monitor (3) that outputs the game screen display, a touch panel (5), and an external memory device (20) that stores sequence data (28) which records the operation timing for touch operation of a touch panel (5). The game system displays an object (60) that corresponds to the operation timing and an operation reference indicator (55) that corresponds to the current time in the game and guides the player's touch operation by reducing the distance between the object (60) and the operation reference indicator (55) according to the difference between the operation timing and the current time and by moving the object (60) such that the object (60) matches the operation reference indicator (55) at the operation timing. The game system also changes the distance between the object (60) and the operation reference indicator (55) in accordance with predetermined conditions.

摘要翻译： 公开了一种游戏系统，包括输出游戏画面显示的监视器（3），触摸面板（5）和存储顺序数据（28）的外部存储装置（20），所述序列数据记录了触摸操作的操作定时 触摸面板（5）。 游戏系统显示对应于操作定时的对象（60）和对应于游戏中的当前时间的操作参考指示符（55），并通过减小对象（60）和对象（60）之间的距离来引导玩家的触摸操作 根据操作时间和当前时间之间的差异，通过移动对象（60）使得对象（60）在操作定时与操作参考指示符（55）匹配的操作参考指示符（55）。 游戏系统还根据预定条件改变对象（60）和操作参考指示符（55）之间的距离。

公开(公告)号：US20130116047A1

公开(公告)日：2013-05-09

申请号：US13702449

申请日：2011-06-10

申请人： Takao Yamamoto ,  Shota Katagiri ,  Masahiro Kiyomoto ,  Yuma Takafuji ,  Mayumi Okuyama ,  Tatsuya Iyama ,  Yoshitaka Nishimura

发明人： Takao Yamamoto ,  Shota Katagiri ,  Masahiro Kiyomoto ,  Yuma Takafuji ,  Mayumi Okuyama ,  Tatsuya Iyama ,  Yoshitaka Nishimura

IPC分类号： A63F13/00

CPC分类号： A63F13/44 ,  A63F13/211 ,  A63F13/2145 ,  A63F2300/1075 ,  A63F2300/638

摘要： A gaming system is provided with a monitor for displaying and outputting a gaming screen, a touch panel superposed upon the monitor, and an external storage device for storing sequence data in which an operational period of the touch panel has been described. In addition, the gaming system displays upon the monitor a gaming area whereupon two reference units disposed apart from each other and a specific reference unit disposed in the vicinity of the reference units are set. Also, an object for instructing operations for each of the reference units is displayed while being caused to move within the gaming area, and in the case of a mis-operation of a specific object heading toward the specific reference unit, the specific object is destroyed, and the path which had been set as the object appearance area is used as the path of movement for the next object.

摘要翻译： 一种游戏系统具有显示和输出游戏画面的显示器，重叠在监视器上的触摸面板，以及外部存储装置，用于存储其中描述了触摸面板的操作周期的顺序数据。 此外，游戏系统在监视器上显示游戏区域，由此设置彼此分离的两个参考单元和设置在参考单元附近的特定参考单元。 此外，在游戏区域中显示用于指示每个参考单元的操作的对象，并且在特定对象朝向特定参考单元的错误操作的情况下，特定对象被破坏 并且将被设置为对象外观区域的路径用作下一个对象的移动路径。