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公开(公告)号:US07502887B2
公开(公告)日:2009-03-10
申请号:US10578314
申请日:2004-09-08
申请人: Tetsuya Tanaka , Hazuki Okabayashi , Ryuta Nakanishi , Tokuzo Kiyohara , Takao Yamamoto , Keisuke Kaneko
发明人: Tetsuya Tanaka , Hazuki Okabayashi , Ryuta Nakanishi , Tokuzo Kiyohara , Takao Yamamoto , Keisuke Kaneko
CPC分类号: G06F12/0842 , G06F12/0848 , G06F12/121 , G06F12/126
摘要: The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.
摘要翻译: 本发明中的高速缓存存储器是N路组相关高速缓冲存储器,其包括表示N路中的一种或多种方式的控制寄存器,激活由所述控制寄存器指示的方式的控制单元和更新单元 所述控制寄存器的内容。 控制单元至少以除由控制寄存器指示的主动方式以外的方式进行更换。
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公开(公告)号:US20090077318A1
公开(公告)日:2009-03-19
申请号:US11910831
申请日:2006-03-17
申请人: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
CPC分类号: G06F12/0875 , G06F12/0848 , G06F12/0888
摘要: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译: 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器,当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时,判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断,以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元,并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。
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公开(公告)号:US07970998B2
公开(公告)日:2011-06-28
申请号:US11910831
申请日:2006-03-17
申请人: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
发明人: Takao Yamamoto , Tetsuya Tanaka , Ryuta Nakanishi , Masaitsu Nakajima , Keisuke Kaneko , Hazuki Okabayashi
IPC分类号: G06F12/08
CPC分类号: G06F12/0875 , G06F12/0848 , G06F12/0888
摘要: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.
摘要翻译: 本发明的高速缓存存储器包括与第一高速缓存存储器并行操作的第二高速缓冲存储器,当在第一高速缓冲存储器和第二高速缓冲存储器两者中发生高速缓存未命中时,判断单元都是真的或 关于存储器访问导致高速缓存未命中的数据的属性的错误判断,以及当进行判断时将存储器数据存储在第二高速缓冲存储器中的控制单元,并且将存储器数据存储在第一高速缓冲存储器中 做出了错误的判断。
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公开(公告)号:US20070186048A1
公开(公告)日:2007-08-09
申请号:US10599170
申请日:2005-03-16
IPC分类号: G06F12/00
CPC分类号: G06F12/0862 , G06F2212/6028
摘要: The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line data, from the memory to the cache memory; and a touch unit 415 which sets the predicted line address to the cache entry, as a tag, and validates the valid flag, without loading data from the memory into the cache memory
摘要翻译: 本发明的高速缓冲存储器包括:预测单元39,其基于从存储器输出的存储器访问的进度,预测下一个预取的行地址。 预测单元39包括:预取单元414,其将预测行数据的数据从存储器预取到高速缓冲存储器; 以及触摸单元415,其将预测线路地址设置为高速缓存条目作为标签,并且验证有效标志,而不将数据从存储器加载到高速缓冲存储器
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公开(公告)号:US07953935B2
公开(公告)日:2011-05-31
申请号:US11816858
申请日:2006-02-08
IPC分类号: G06F13/00
CPC分类号: G06F12/12 , G06F12/0802 , G06F12/0893
摘要: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译: 容易接受用于处理的软件控制的高速缓冲存储器系统包括:设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC(传送和属性控制器)。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标,以便请求针对该地址的命令所指示的操作 高速缓存存储器。
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公开(公告)号:US20090100231A1
公开(公告)日:2009-04-16
申请号:US11816858
申请日:2006-02-08
IPC分类号: G06F12/08
CPC分类号: G06F12/12 , G06F12/0802 , G06F12/0893
摘要: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.
摘要翻译: 容易接受用于处理的软件控制的高速缓冲存储器系统包括:设置在处理器和存储器之间的高速缓存存储器; 以及用于控制高速缓冲存储器的TAC(传送和属性控制器)。 TAC接收指示由处理器执行预定指令而产生的高速缓存数据的传送和属性操作以及用于操作的目标,以便请求针对该地址的命令所指示的操作 高速缓存存储器。
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公开(公告)号:US20080046687A1
公开(公告)日:2008-02-21
申请号:US11896368
申请日:2007-08-31
申请人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
CPC分类号: G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
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公开(公告)号:US07594099B2
公开(公告)日:2009-09-22
申请号:US11896368
申请日:2007-08-31
申请人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号: G06F9/305
CPC分类号: G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译: 根据本发明的处理器包括解码单元20,操作单元40等。 当解码单元20解码指令vcchk时,操作单元40等判断条件标志寄存器(CFR)32的矢量条件标志VC0〜VC3(110)全部为零,并且(i)设置条件标志C4 当所有向量条件标志VC0〜VC3都为零时,分别将条件标志寄存器(CFR)32至1和0分别设置为条件标志寄存器(CFR)32和C5,以及(ii)分别将条件标志C4和C5设置为0和1, 并非所有向量条件标志都为零。 然后,矢量条件标志VC0〜VC3被存储在条件标志C0〜C3中。
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公开(公告)号:US20080046704A1
公开(公告)日:2008-02-21
申请号:US11896371
申请日:2007-08-31
申请人: Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人: Tetsuya Tanaka , Hazuki OKabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
IPC分类号: G06F9/38
CPC分类号: G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译: 根据本发明的处理器包括解码单元20,操作单元40等。 当解码单元20解码指令vcchk时,操作单元40等判断条件标志寄存器(CFR)32的矢量条件标志VC 0〜VC 3(110)是否全部为零,以及(i)设置条件 当所有向量条件标志VC 0〜VC 3都为零时,分别为条件标志寄存器(CFR)32〜1和0的标志C 4和C 5,(ii)设定条件标志C 4和C 5 分别为0和1,当不是全部矢量条件标志为零时。 然后,矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。
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公开(公告)号:US20080046688A1
公开(公告)日:2008-02-21
申请号:US11896369
申请日:2007-08-31
申请人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
发明人: Tetsuya Tanaka , Hazuki Okabayashi , Taketo Heishi , Hajime Ogawa , Tsuneyuki Suzuki , Tokuzo Kiyohara , Takeshi Tanaka , Hideshi Nishida , Masaki Maeda
CPC分类号: G06F9/30025 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30094 , G06F9/30145 , G06F9/3016 , G06F9/30167
摘要: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.
摘要翻译: 根据本发明的处理器包括解码单元20,操作单元40等。 当解码单元20解码指令vcchk时,操作单元40等判断条件标志寄存器(CFR)32的矢量条件标志VC 0〜VC 3(110)是否全部为零,以及(i)设置条件 当所有向量条件标志VC 0〜VC 3都为零时,分别为条件标志寄存器(CFR)32〜1和0的标志C 4和C 5,(ii)设定条件标志C 4和C 5 分别为0和1,当不是全部矢量条件标志为零时。 然后,矢量条件标志VC 0〜VC 3被存储在条件标志C 0〜C 3中。
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