公开(公告)号：US07673265B2

公开(公告)日：2010-03-02

申请号：US11851058

申请日：2007-09-06

申请人： Takashi Akiba ,  Takashi Miura

发明人： Takashi Akiba ,  Takashi Miura

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022

摘要： A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established.

摘要翻译： 一种模拟装置，包括分配操作周期数的第一模拟器，分配操作周期数的第二模拟器和用于同步控制第一模拟器和第二模拟器的控制部分，所述控制部分引起第一模拟器与第二模拟器之间的通信 模拟器，以便控制第一模拟器和第二模拟器的控制信息和同步信息，第一模拟器和第二模拟器的控制信息控制操作，其中控制部分设置第一模拟器的操作周期数 并且当所述同步信息的同步状态被建立时，所述第二模拟器处于第一周期值，所述控制部分以第二周期值设定所述第一模拟器和所述第二模拟器的操作周期数中的至少一个， 同步信息的同步状态时的第一个周期值 没有建立。

公开(公告)号：US20090204384A1

公开(公告)日：2009-08-13

申请号：US12367761

申请日：2009-02-09

申请人： Takashi AKIBA ,  Takashi Miura

发明人： Takashi AKIBA ,  Takashi Miura

IPC分类号： G06F9/455

CPC分类号： G06F11/3652

摘要： A hardware emulator having: a verification target circuit that includes a CPU in which progress of instruction execution is controlled by a program counter, and a circuit that operates according to the instruction execution by the CPU; at least one replica circuit that is formed by replication of the verification target circuit; a debug controller that starts operation of the verification target circuit upon receipt of an operation start signal from an outside of the hardware emulator, and that stops operation of the verification target circuit and the replica circuit when a value of the program counter of the verification target circuit reaches a predetermined breakpoint; an execution start delaying portion that causes the replica circuit to start execution of an instruction with a delay equivalent to a predetermined number of instructions after the verification target circuit starts execution of the same instruction; a program counter controller that performs control so that the value of the program counter of the verification target circuit and a value of a program counter of the replica circuit are simultaneously updated when both of the verification target circuit and the replica circuit complete the execution of their respective running instructions; and an output portion that sends an output from any one of the verification target circuit and the replica circuit to the outside of the hardware emulator in response to a request from the outside of the hardware emulator.

摘要翻译： 一种硬件仿真器，具有：验证对象电路，包括CPU，其中由程序计数器控制指令执行的进行，以及根据CPU的指令执行操作的电路; 由验证对象电路的复制形成的至少一个复制电路; 调试控制器，当从所述硬件仿真器的外部接收到操作开始信号时，开始所述验证对象电路的动作，并且当所述验证对象的程序计数器的值为止时，停止所述验证对象电路和所述副本电路的动作 电路达到预定的断点; 一个执行开始延迟部分，在验证目标电路开始执行相同的指令之后，使得复制电路开始执行具有等于预定数目的指令的延迟的指令; 程序计数器控制器，当验证对象电路和复制电路两者完成其执行时，进行控制，使得验证对象电路的程序计数器的值和复制电路的程序计数器的值同时被更新 各自运行指令; 以及输出部，其响应于来自硬件仿真器的外部的请求，将来自验证对象电路和复制电路中的任一个的输出发送到硬件仿真器的外部。

公开(公告)号：US20080312900A1

公开(公告)日：2008-12-18

申请号：US12133061

申请日：2008-06-04

申请人： Takashi AKIBA ,  Takashi Miura

发明人： Takashi AKIBA ,  Takashi Miura

IPC分类号： G06F9/455

CPC分类号： G06F9/455 ,  G06F11/3632 ,  G06F11/3652 ,  G06F11/3656

摘要： According to the present invention, there is provided a simulation apparatus having, a hardware emulator which includes a first CPU core as a simulation target, and a debug control unit; a software simulator which includes a second CPU core as a simulation target, and a clock generation unit which generates a clock and supplies the clock to the first CPU core and the second CPU core; and a debugger which debugs the first CPU core and the second CPU core and in which a clock disable condition is set, wherein upon determining that the clock disable condition set in the debugger is satisfied, the debug control unit outputs a clock disable signal, and upon receiving the clock disable signal, the clock generation unit stops generating the clock.

摘要翻译： 根据本发明，提供了一种模拟装置，具有包括作为模拟目标的第一CPU核心的硬件仿真器和调试控制单元; 包括作为模拟目标的第二CPU核心的软件模拟器和产生时钟并将时钟提供给第一CPU内核和第二CPU内核的时钟生成单元; 以及调试器，其对所述第一CPU核心和所述第二CPU核心进行调试，并且其中设置了时钟禁止条件，其中，当确定调试器中设置的时钟禁止条件被满足时，所述调试控制单元输出时钟禁止信号，以及 在接收到时钟禁止信号时，时钟产生单元停止产生时钟。

公开(公告)号：US20090083682A1

公开(公告)日：2009-03-26

申请号：US11851058

申请日：2007-09-06

申请人： Takashi Akiba ,  Takashi Miura

发明人： Takashi Akiba ,  Takashi Miura

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A simulation apparatus, including a first simulator assigning an operating cycle number, a second simulator assigning an operating cycle number, and a control portion for synchronously controlling the first simulator and the second simulator, the control portion causing communication between the first simulator and the second simulator so as to control control-information and synchronous-information of the first simulator and the second simulator, the control-information controlling operations of the first simulator and the second simulator, wherein the control portion sets up the operating cycle numbers of the first simulator and the second simulator at a first cycle value when a synchronous condition of the synchronous-information is established, the control portion sets up at least one of the operating cycle numbers of the first simulator and the second simulator at a second cycle value being larger than the first cycle value when the synchronous condition of the synchronous-information is not established.

摘要翻译： 一种模拟装置，包括分配操作周期数的第一模拟器，分配操作周期数的第二模拟器和用于同步控制第一模拟器和第二模拟器的控制部分，所述控制部分引起第一模拟器与第二模拟器之间的通信 模拟器，以便控制第一模拟器和第二模拟器的控制信息和同步信息，第一模拟器和第二模拟器的控制信息控制操作，其中控制部分设置第一模拟器的操作周期数 并且当所述同步信息的同步状态被建立时，所述第二模拟器处于第一周期值，所述控制部分以第二周期值设定所述第一模拟器和所述第二模拟器的操作周期数中的至少一个， 同步信息的同步状态时的第一个周期值 没有建立。

公开(公告)号：US08312162B2

公开(公告)日：2012-11-13

申请号：US12869153

申请日：2010-08-26

申请人： Tsuyoshi Honma ,  Akihiko Kinoshita ,  Hiroyuki Chiba ,  Takashi Miura

发明人： Tsuyoshi Honma ,  Akihiko Kinoshita ,  Hiroyuki Chiba ,  Takashi Miura

IPC分类号： G06F15/16

CPC分类号： H04L29/08729 ,  H04L67/2819 ,  H04N21/42661 ,  H04N21/44004 ,  H04N21/44209 ,  H04N21/458 ,  H04N21/8456

摘要： There is provided an information processing apparatus including a communication unit which communicates with a distribution server that contains content data for streaming delivery, a buffer unit which temporarily stores stream data obtained from the distribution server, a storage unit which stores an inserting content, a reproduction unit which reproduces the content inserted by the storage unit, and a control unit which measures a bandwidth of the network, determines whether it is possible to reproduce until the end of a next chapter defined by a chapter point set in the content based on a buffer volume of the buffer unit and the bandwidth, and when determined it is impossible, switches the content to be produced by the reproduction unit to the inserting content.

摘要翻译： 提供了一种信息处理设备，包括：通信单元，其与包含用于流传送的内容数据的分发服务器进行通信;临时存储从分发服务器获得的流数据的缓冲单元，存储插入内容的存储单元， 再现由存储单元插入的内容的单元和测量网络带宽的控制单元，确定是否可以再现直到由基于缓冲器的内容中设置的章节点定义的下一章节的结尾 缓冲单元的体积和带宽，并且当确定不可能时，将由再现单元产生的内容切换到插入内容。

公开(公告)号：US08007174B2

公开(公告)日：2011-08-30

申请号：US11793519

申请日：2005-06-06

申请人： Madoka Yamaguchi ,  Masahiro Akioka ,  Mutsushi Hirano ,  Kenji Yoshihiro ,  Takashi Miura

发明人： Madoka Yamaguchi ,  Masahiro Akioka ,  Mutsushi Hirano ,  Kenji Yoshihiro ,  Takashi Miura

IPC分类号： B65D33/10 ,  B65D33/00 ,  B65D33/16 ,  B65D30/16

CPC分类号： A61J1/2093 ,  A61J1/10 ,  B65D33/2525 ,  B65D33/2533 ,  B65D75/008 ,  B65D75/566 ,  B65D75/5805 ,  B65D75/5883 ,  B65D2575/565 ,  Y10S383/906

摘要： A bag-like container with a spout in which a plastic linear fastener is interposed in an upper part of the container so that when water content or the like is to be supplied after contents of a liquid food container or the like have been administered to a subject, opening and closing the linear fastener enables the water content or the like to be supplied in an uncomplicated manner without the use of a separate member such as a spout that is an open part for pouring food, water, or the like into the container.

摘要翻译： 具有喷口的袋状容器，其中塑料线性紧固件插入容器的上部，使得当向液体食品容器等的内容物施用水分或类似物之后， 主体，打开和关闭线性紧固件使得能够以不复杂的方式供应含水量，而不需要使用诸如作为将食品，水等倾入容器的开放部分的喷嘴的单独构件 。

公开(公告)号：US20110078324A1

公开(公告)日：2011-03-31

申请号：US12869153

申请日：2010-08-26

申请人： Tsuyoshi HONMA ,  Akihiko Kinoshita ,  Hiroyuki Chiba ,  Takashi Miura

发明人： Tsuyoshi HONMA ,  Akihiko Kinoshita ,  Hiroyuki Chiba ,  Takashi Miura

IPC分类号： G06F15/16

CPC分类号： H04L29/08729 ,  H04L67/2819 ,  H04N21/42661 ,  H04N21/44004 ,  H04N21/44209 ,  H04N21/458 ,  H04N21/8456

摘要： There is provided an information processing apparatus including a communication unit which communicates with a distribution server that contains content data for streaming delivery, a buffer unit which temporarily stores stream data obtained from the distribution server, a storage unit which stores an inserting content, a reproduction unit which reproduces the content inserted by the storage unit, and a control unit which measures a bandwidth of the network, determines whether it is possible to reproduce until the end of a next chapter defined by a chapter point set in the content based on a buffer volume of the buffer unit and the bandwidth, and when determined it is impossible, switches the content to be produced by the reproduction unit to the inserting content.

摘要翻译： 提供了一种信息处理设备，包括：通信单元，其与包含用于流传送的内容数据的分发服务器进行通信;临时存储从分发服务器获得的流数据的缓冲单元，存储插入内容的存储单元， 再现由存储单元插入的内容的单元和测量网络带宽的控制单元，确定是否可以再现直到由基于缓冲器的内容中设置的章节点定义的下一章节的结尾 缓冲单元的体积和带宽，并且当确定不可能时，将由再现单元产生的内容切换到插入内容。

公开(公告)号：US07280839B2

公开(公告)日：2007-10-09

申请号：US10531051

申请日：2003-12-26

申请人： Takashi Miura ,  Hidenori Matsumoto ,  Toshio Obara

发明人： Takashi Miura ,  Hidenori Matsumoto ,  Toshio Obara

IPC分类号： H04Q7/20

CPC分类号： H04W52/04

摘要： It is an object of the present invention to suppress an abrupt gain change and smoothly and highly accurately control transmitted electric power even if the transmitted electric power greatly changes when a closed loop control that crosses the threshold value as the detection limit of the transmitted electric power.The transmitted electric power of a self-station is detected to obtain an error between the detected transmitted electric power of the self-station and transmitted electric power set in accordance with a transmitted electric power control bit sent to the self-station from the other station. A buffer unit such as a transmitted electric power deciding part, an error integrating part or the like is provided for preventing the obtained error from greatly changing upon great change of the transmitted electric power when the transmitted electric power is controlled by crossing the threshold value as the detection limit of the transmitted electric power. Thus, an error when the gain of the variable gain amplifier is suppressed.

摘要翻译： 本发明的目的是抑制突然的增益变化，并且即使当跨越阈值的闭环控制作为发送电力的检测极限时，即使发送的电力发生大的变化，也能够平滑高精度地控制发送的电力 。 检测自站的发射功率，以便根据从另一台站发送到自车站的发射功率控制比特来获得检测到的自站发射功率与发射功率之间的误差 。 提供诸如发送功率决定部分，误差积分部分等的缓冲单元，用于当通过将阈值作为跨越阈值进行控制来防止所发送的电力发生大的变化时所获得的误差的大幅度变化 传输电力的检测限。 因此，抑制可变增益放大器的增益时的误差。

公开(公告)号：US06407293B1

公开(公告)日：2002-06-18

申请号：US09962122

申请日：2001-09-26

申请人： Akira Amano ,  Teruyoshi Akiyama ,  Takashi Miura ,  Toshimitsu Hagiwara

发明人： Akira Amano ,  Teruyoshi Akiyama ,  Takashi Miura ,  Toshimitsu Hagiwara

IPC分类号： C07C3512

CPC分类号： C07C43/196 ,  C07C41/03

摘要： A process for producing highly pure 3-1-menthoxypropane-1,2-diol safely and efficiently, and an intermediate to be used in the process. 3-1-menthoxypropane-1,2-diol represented by the chemical formula (IV) is produced by adding 1-menthol to a 1,2-epoxy-3-halogenopropane represented by the following general formula (I) (wherein X represents a halogen atom) in an organic solvent in the presence of a Lewis acid to produce a novel 1-halogeno-3-1-menthoxypropan-2-ol represented by the following general formula (II), then, epoxidating it with a base in the presence of a phase transfer catalyst to produce a 1,2-epoxy-3-1-menthoxypropane represented by the chemical formula (III), and further hydrolyzing it.

摘要翻译： 安全有效地生产高纯度3-1-薄荷氧基丙二醇-1,2-二醇的方法，以及该方法中使用的中间体。 由化学式（IV）表示的3-1-薄荷氧基丙烷-1,2-二醇通过将1-薄荷醇加入到由下列通式（I）表示的1,2-环氧-3-氯代丙烷中（其中X表示 卤素原子）在有机溶剂中在路易斯酸存在下反应，得到由以下通式（II）表示的新型1-卤代-3-三氟甲氧基丙-2-醇，然后用碱进行环氧化 存在相转移催化剂以制备由化学式（III）表示的1,2-环氧-3-丁氧基丙烷，并进一步水解。

公开(公告)号：US06340751B1

公开(公告)日：2002-01-22

申请号：US09357153

申请日：1999-07-19

申请人： Takao Saito ,  Toshiyuki Murayama ,  Takaji Matsumoto ,  Takashi Miura

发明人： Takao Saito ,  Toshiyuki Murayama ,  Takaji Matsumoto ,  Takashi Miura

IPC分类号： C07F718

CPC分类号： C07D413/06 ,  C07D205/08 ,  Y02P20/55

摘要： Disclosed is a process for the preparation of a 4-substituted azetidinone derivative, which comprises reacting an azetidinone derivative and an amide compound in the presence of a magnesium compound such as those represented by the following formulas (II): and (IV): represented by the following formula (III): MgR5R6  (III) wherein R5 represents a C1-12 alkyl group, a C2-5 alkenyl group, a 5- to 8-membered alicyclic group which may be substituted by a lower C1-4 alkyl group, a phenyl group which may be substituted by a lower C1-4 alkyl group, a lower C1-4 alkoxy group or a halogen atom or a benzyl group which may be substituted by a lower C1-4 alkyl group, a lower C1-4 alkoxy group or a halogen atom, and R6 represents a halogen atom, a methanesulfonyloxy group, a benzenesulfonyloxy group, a p-toluenesulfonyloxy group, a trifluoromethanesulfonyloxy group, an acetoxy group which may be substituted by a halogen atom or a cyano group or an OR7 group (R7 representing a lower C1-4 alkyl group, a substituted or unsubstituted phenyl group or a substituted or unsubstituted benzyl group). The process provides an industrially excellent process for the preparation of a 4-substituted azetidinone derivative which permits the selective preparation of an intermediate for the synthesis of a carbapenem antibacterial agent having a desired 1-&bgr;′ configuration.

摘要翻译： 公开了制备4-取代的氮杂环丁酮衍生物的方法，该方法包括在镁化合物如下式（II）和（IV）所示的那些镁化合物存在下使氮杂环丁酮衍生物与酰胺化合物反应：代表 通过下式（III）表示：其中R5表示C1-12烷基，C2-5烯基，可被低级C1-4烷基取代的5至8元脂环基，苯基 可以被低级C 1-4烷基，低级C 1-4烷氧基或卤素原子取代的苯基，或可以被低级C 1-4烷基取代的苄基，低级C 1-4烷氧基或 卤原子，R6表示卤原子，甲磺酰氧基，苯磺酰氧基，对甲苯磺酰氧基，三氟甲磺酰氧基，可被卤素原子或氰基取代的乙酰氧基或OR7基（R7表示 低级C 1-4烷基，取代的o R未取代的苯基或取代或未取代的苄基）。 该方法提供了制备4-取代的氮杂环丁酮衍生物的工业上优异的方法，其允许选择性制备用于合成具有所需1-β'构型的碳青霉烯类抗菌剂的中间体。