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    Semiconductor device and drive circuit using the semiconductor devices
    2.
    发明授权
    Semiconductor device and drive circuit using the semiconductor devices 失效
    使用半导体器件的半导体器件和驱动电路

    公开(公告)号：US06956255B2

    公开(公告)日：2005-10-18

    申请号：US10289306

    申请日：2002-11-07

    申请人： Eiji Oue ,  Katsuyoshi Washio ,  Masao Kondo ,  Hiromi Shimamoto

    发明人： Eiji Oue ,  Katsuyoshi Washio ,  Masao Kondo ,  Hiromi Shimamoto

    IPC分类号： H01L21/331 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8249 ,  H01L23/367 ,  H01L27/04 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/786 ,  H01L29/80 ,  H01L39/112

    CPC分类号： H01L29/7322 ,  H01L21/8249 ,  H01L23/3677 ,  H01L29/7317 ,  H01L2224/82 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A high-speed bipolar transistor is provided which is improved in the effect of heat radiation without increasing the substrate capacitance. The heat radiation connection between a base region and a silicon substrate includes a p+ extrinsic base polysilicon electrode and a polysilicon layer buried in an isolation groove with a very thin silicon dioxide side wall. Accordingly, the heat generated at the base is radiated through this path to the silicon substrate. Further, the film thickness of the silicon dioxide on the inner wall of the isolation groove is sufficiently increased compared with previous structures to prevent an increase in the substrate capacitance. Consequently, there can be obtained a bipolar transistor which operates at high speed, and is improved in the effect of heat radiation without increasing the substrate capacitance.

    摘要翻译： 提供了高速双极晶体管，其在不增加衬底电容的情况下改善了散热的效果。 基极区域和硅衬底之间的热辐射连接包括一个非本征基极多晶硅电极和一个埋在具有非常薄的二氧化硅侧壁的隔离槽中的多晶硅层。 因此，在基底处产生的热量通过该路径被辐射到硅衬底。 此外，与以前的结构相比，隔离槽的内壁上的二氧化硅的膜厚度充分增加，以防止衬底电容的增加。 因此，可以获得高速工作的双极晶体管，并且在不增加衬底电容的情况下提高散热的效果。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    5.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06476450B2

    公开(公告)日：2002-11-05

    申请号：US09808952

    申请日：2001-03-16

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L29732

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    7.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06815822B2

    公开(公告)日：2004-11-09

    申请号：US10237705

    申请日：2002-09-10

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L2348

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。

    Information processing apparatus, information processing system and information processing method
    10.
    发明授权
    Information processing apparatus, information processing system and information processing method 有权
    信息处理装置，信息处理系统和信息处理方法

    公开(公告)号：US09013535B2

    公开(公告)日：2015-04-21

    申请号：US13876294

    申请日：2011-10-03

    申请人： Yusuke Sakai ,  Masao Kondo

    发明人： Yusuke Sakai ,  Masao Kondo

    IPC分类号： H04N7/15 ,  G06F3/042 ,  H04N7/14

    CPC分类号： H04N7/147 ,  G06F3/017 ,  G06F3/042 ,  H04N7/15

    摘要： An information processing apparatus may include a detecting unit to detect a pointing object in a captured image, and a generation unit to generate pointing information based on detection of the pointing object by the detecting unit. The pointing information may indicate a position of the pointing object determined using a pointable range set based on a user in the captured image. The apparatus may further include a communication unit to transmit the pointing information to an external apparatus.

    摘要翻译： 信息处理装置可以包括：检测单元，用于检测拍摄图像中的指示对象;以及生成单元，用于基于检测单元对指示对象的检测来生成指点信息。 指示信息可以指示使用基于捕获图像中的用户设置的可点位范围来确定的指向对象的位置。 该装置还可以包括将指向信息发送到外部设备的通信单元。