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公开(公告)号：US08767881B2
公开(公告)日：2014-07-01
申请号：US13236706
申请日：2011-09-20
申请人： Takashi Yokokawa , Ryoji Ikegaya , Yuji Shinohara
发明人： Takashi Yokokawa , Ryoji Ikegaya , Yuji Shinohara
CPC分类号： H04L1/0047 , H04L1/0019 , H04L1/0057 , H04L1/0071 , H04L27/38 , H04L2001/0093
摘要： A signal processing apparatus is disclosed which includes: a detection section configured such that based on a result of the error correction of a signal generated by a single carrier system, the detection section detects the presence or absence of spectrum inversion in the signal; and a selection section configured such that if the detection section detects the spectrum inversion, the selection section selects the spectrally inverted signal as the signal subject to the error correction, and that if the detection section does not detect the spectrum inversion, then the selection selects the spectrally uninverted signal as the signal subject to the error correction.
摘要翻译： 公开了一种信号处理装置，包括：检测部，被配置为基于由单载波系统生成的信号的纠错结果，检测部检测信号中是否存在频谱反转; 以及选择部分，其被配置为使得如果检测部分检测到频谱反转，则选择部分选择频谱反转的信号作为经过纠错的信号，并且如果检测部分没有检测到频谱反转，则选择选择 作为经过纠错的信号的光谱未反相信号。
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公开(公告)号：US08578237B2
公开(公告)日：2013-11-05
申请号：US12744400
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/036 , H03M13/255 , H03M13/2703 , H03M13/271 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3416 , H04L27/3488
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.
摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。
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公开(公告)号：US08499214B2
公开(公告)日：2013-07-30
申请号：US12743398
申请日：2008-11-26
IPC分类号： H03M13/00
CPC分类号： H04L27/2647 , H03M13/033 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/356 , H03M13/6552 , H03M13/6555
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.
摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。
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4.发明申请公开(公告)号：US20100080316A1
公开(公告)日：2010-04-01
申请号：US12568783
申请日：2009-09-29
CPC分类号： H04L27/2656 , H04L27/2665
摘要： Disclosed herein is an information processing apparatus including: a demodulation FFT processing section configured to carry out an FFT process on a demodulation-related signal extracted by making use of a demodulation FFT window from every symbol of a received OFDM signal and output the frequency-domain signal; a control FFT processing section configured to carry out a process equivalent to an FFT process on a control-related signal extracted by making use of a control FFT window from every symbol of the received OFDM signal and output the frequency-domain signal; a transmission-line information estimation section; an equalization section; a reception-quality computation/comparison section; and an FFT-window position control section configured to control the demodulation FFT window to be used by the demodulation FFT processing section and the control FFT window to be used by the control FFT processing section on the basis of a comparison result produced by the reception-quality computation/comparison section.
摘要翻译： 这里公开了一种信息处理装置，包括：解调FFT处理部，被配置为对通过使用来自接收的OFDM信号的每个符号的解调FFT窗口提取的解调相关信号执行FFT处理，并输出频域 信号; 控制FFT处理部，被配置为执行与通过利用来自所接收的OFDM信号的每个符号的控制FFT窗口提取的控制相关信号上的FFT处理相当的处理，并输出频域信号; 传输线信息估计部; 均衡部分 接收质量计算/比较部分; FFT窗口位置控制部分，被配置为基于由接收模式产生的比较结果来控制由解调FFT处理部分使用的解调FFT窗口和要由控制FFT处理部件使用的控制FFT窗口， 质量计算/比较部分。
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5.发明授权公开(公告)号：US08279956B2
公开(公告)日：2012-10-02
申请号：US12568783
申请日：2009-09-29
IPC分类号： H04K1/10
CPC分类号： H04L27/2656 , H04L27/2665
摘要： Disclosed herein is an information processing apparatus including: a demodulation FFT processing section configured to carry out an FFT process on a demodulation-related signal extracted by making use of a demodulation FFT window from every symbol of a received OFDM signal and output the frequency-domain signal; a control FFT processing section configured to carry out a process equivalent to an FFT process on a control-related signal extracted by making use of a control FFT window from every symbol of the received OFDM signal and output the frequency-domain signal; a transmission-line information estimation section; an equalization section; a reception-quality computation/comparison section; and an FFT-window position control section configured to control the demodulation FFT window to be used by the demodulation FFT processing section and the control FFT window to be used by the control FFT processing section on the basis of a comparison result produced by the reception-quality computation/comparison section.
摘要翻译： 这里公开了一种信息处理装置，包括：解调FFT处理部，被配置为对通过使用来自接收的OFDM信号的每个符号的解调FFT窗口提取的解调相关信号执行FFT处理，并输出频域 信号; 控制FFT处理部，被配置为执行与通过利用来自所接收的OFDM信号的每个符号的控制FFT窗口提取的控制相关信号上的FFT处理相当的处理，并输出频域信号; 传输线信息估计部; 均衡部分 接收质量计算/比较部分; FFT窗口位置控制部分，被配置为基于由接收模式产生的比较结果来控制由解调FFT处理部分使用的解调FFT窗口和要由控制FFT处理部件使用的控制FFT窗口， 质量计算/比较部分。
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公开(公告)号：US20120110415A1
公开(公告)日：2012-05-03
申请号：US13238397
申请日：2011-09-21
申请人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
发明人： Takashi Yokokawa , Osamu Shinya , Yutaka Nakada , Ryoji Ikegaya
CPC分类号： H03M13/152 , H03M13/65 , H03M13/6502
摘要： The present disclosure provides a decoding apparatus including, a storage section configured to store a reception value, a detection section configured to detect an error in the reception value, an error correction section configured to correct an error detected by the detection section with respect to the reception value, and a control section configured to control reading of the reception value from the storage section, wherein the control section controls first reading such that the reception value is read into the detection section and, after detection of an error by the detection section, second reading such that substantially the same reception value as that in the first reading is read into the error correction section.
摘要翻译： 本公开提供了一种解码装置，包括：存储部，被配置为存储接收值;检测部，被配置为检测接收值中的误差;纠错部，被配置为校正由所述检测部检测到的相对于 接收值，以及控制部，其被配置为控制从所述存储部读取接收值，其中，所述控制部控制第一读取，使得所述接收值被读入所述检测部，并且在检测部检测到错误之后， 第二读取使得与第一读取中基本上相同的接收值被读入错误校正部分。
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7.发明申请DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD 有权数据处理设备和数据处理方法，如编码设备和编码方法公开(公告)号：US20100299572A1
公开(公告)日：2010-11-25
申请号：US12743649
申请日：2008-11-18
CPC分类号： H04L27/3416 , H03M13/036 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/356 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3488 , H04L27/36
摘要： A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of ⅔, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.
摘要翻译： 可以应用于例如用于发送LDPC码等的传输系统的数据处理装置，数据处理方法，编码装置和编码方法，并且可以提高对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和an的编码率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。
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公开(公告)号：US20100275101A1
公开(公告)日：2010-10-28
申请号：US12744400
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
CPC分类号： H03M13/1165 , H03M13/036 , H03M13/255 , H03M13/2703 , H03M13/271 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3416 , H04L27/3488
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed.
摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中取代mb比特，并将替换后的码比特设置为b符号的符号比特。 根据分配规则，分别将代码比特和符号比特的组合作为码比特组和符号比特组分别设定为组合的任何编码比特组 以及要分配码位组的码位的符号位的符号位组，以及代码位和符号位的位编号。
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9.发明授权Data processing apparatus and data processing method as well as encoding apparatus and encoding method 有权数据处理装置和数据处理方法以及编码装置和编码方法公开(公告)号：US08335964B2
公开(公告)日：2012-12-18
申请号：US12743384
申请日：2008-11-25
IPC分类号： G06F11/00
CPC分类号： H04L27/3416 , H03M13/036 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/356 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3488 , H04L27/36
摘要： A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.
摘要翻译： 可以应用于例如用于发送LDPC码的传输系统等的数据处理装置，数据处理方法，编码装置和编码方法，并且可以改善对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和2/3的编码速率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。
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公开(公告)号：US20100269019A1
公开(公告)日：2010-10-21
申请号：US12743398
申请日：2008-11-26
CPC分类号： H04L27/2647 , H03M13/033 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/356 , H03M13/6552 , H03M13/6555
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.
摘要翻译： 数据处理装置和数据处理方法技术领域本发明涉及一种数据处理装置和数据处理方法，其可以提高对数据的误差的容忍度。 解复用器25根据用于分配LDPC码的码位的分配规则替换代表码元的符号位，并从代码比特中替换mb比特，并将替换后的码比特设置为b符号的符号比特。 例如，当m为12且b为1时，其中来自12×1码位的最高有效位的第i + 1位和一个符号的12×1符号位表示为位bi和yi，替换为 分配例如b0至y8，b1至y0，b2至y6，b3至y1，b4至y4，b5至y5，b6至y2，b7至y3，b8至y7，b9至y10，b10至y11和b11 到y9进行。 本发明可以应用于例如用于发送LDPC码等的传输系统。
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