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公开(公告)号：US07203113B2
公开(公告)日：2007-04-10
申请号：US11090151
申请日：2005-03-28
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.
摘要翻译： 公开了一种半导体存储装置，其中以这样的方式执行控制，即如果当芯片选择信号从不活动（待机）状态转换到活动状态时不执行刷新操作，则读取或写入访问是 立即执行，并且当芯片选择信号经历从非活动状态转换到活动状态时刷新操作正在进行时，等待发生电路产生用于使读或写访问等待的等待信号。
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公开(公告)号：US06925016B2
公开(公告)日：2005-08-02
申请号：US10467031
申请日：2002-01-30
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then, a request for entry of operation mode is accepted. In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US20050105380A1
公开(公告)日：2005-05-19
申请号：US10985876
申请日：2004-11-12
IPC分类号： G11C11/407 , G11C5/06 , G11C8/00
CPC分类号： G11C5/066
摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.
摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。
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公开(公告)号：US07184322B2
公开(公告)日：2007-02-27
申请号：US10985876
申请日：2004-11-12
CPC分类号： G11C5/066
摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.
摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。
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5.发明授权公开(公告)号：US07145812B2
公开(公告)日：2006-12-05
申请号：US11133974
申请日：2005-05-20
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry.If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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6.发明申请公开(公告)号：US20050216676A1
公开(公告)日：2005-09-29
申请号：US11133974
申请日：2005-05-20
IPC分类号： G11C11/401 , G11C7/10 , G11C11/403 , G11C11/406 , G06F13/00
CPC分类号： G11C7/1045
摘要： There is provided a method of entry of an operation mode of a semiconductor memory during operations without need of any specific timing specification and with effective suppression to any erroneous entry. If read cycles for plural addresses are continued, then a request for entry of operation mode is accepted (steps S1 and S2). In write cycles following to those read cycles, an operation mode to be entered is decided based on data externally designated, wherein in the first write cycle, the kind of the operation mode is set, and then in the next write cycle, conditions for the operation mode are set for the entry of the operation mode of the semiconductor memory.
摘要翻译： 提供了一种在操作期间输入半导体存储器的操作模式的方法，而不需要任何特定的时序指定并有效抑制任何错误的输入。 如果持续多个地址的读取周期，则接受进入操作模式的请求（步骤S1和S2）。 在这些读取周期之后的写入周期中，基于外部指定的数据来决定要输入的操作模式，其中在第一写入周期中，设置操作模式的种类，然后在下一个写入周期中， 操作模式被设置用于输入半导体存储器的操作模式。
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公开(公告)号：US06556482B2
公开(公告)日：2003-04-29
申请号：US09872291
申请日：2001-06-01
IPC分类号： G11C1604
CPC分类号： G11C8/06 , G11C7/22 , G11C8/18 , G11C11/4082 , G11C11/419
摘要： According to the disclosed embodiments, a semiconductor memory device may include an address register circuit (406) and data register circuit (411) that can store a write address and write data from one write operation and output the stored write address and write data during a subsequent write operation. In a dynamic random access memory (DRAM) embodiment (400), a precharge and/or refresh operation may follow the writing of previously stored write data. Such an arrangement may reduce and/or eliminate a read after write timing requirement (TWR), which can improve the operating speed of the semiconductor memory device.
摘要翻译： 根据所公开的实施例，半导体存储器件可以包括地址寄存器电路（406）和数据寄存器电路（411），其可以存储来自一个写入操作的写入地址和写入数据，并在一个写入操作期间输出存储的写入地址和写入数据 后续写操作。 在动态随机存取存储器（DRAM）实施例（400）中，预充电和/或刷新操作可以跟随先前存储的写入数据的写入。 这种布置可以减少和/或消除写时序要求（TWR）之后的读取，这可以提高半导体存储器件的操作速度。
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公开(公告)号：US20050219930A1
公开(公告)日：2005-10-06
申请号：US11090151
申请日：2005-03-28
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C11/409
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.
摘要翻译： 公开了一种半导体存储装置，其中以这样的方式执行控制，即如果当芯片选择信号经历从非活动（待机）状态转换到活动状态时不执行刷新操作，则读或写访问是 立即执行，并且当芯片选择信号经历从非活动状态转换到活动状态时刷新操作正在进行时，等待发生电路产生用于使读或写访问等待的等待信号。
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公开(公告)号：US20220315830A1
公开(公告)日：2022-10-06
申请号：US17693781
申请日：2022-03-14
申请人： Naoki URA , Hiroyuki Takahashi
发明人： Naoki URA , Hiroyuki Takahashi
IPC分类号： C09K9/02 , G02F1/155 , G02F1/1516 , G02F1/1523
摘要： Provided is an electrochromic display element including a first substrate, a first electrode over the first substrate, a first electrochromic layer over the first electrode, an electrolyte layer over the first electrochromic layer, a second electrode over the electrolyte layer, and a second substrate over the second electrode. The first electrochromic layer contains tin oxide having an average primary particle diameter of less than 30 nm and an electrochromic compound containing a functional group bindable to the tin oxide. The amount by mole of the electrochromic compound per area of the first electrochromic layer is from 2.0×10−8 mol/cm2 through 2.0×10−7 mol/cm2.
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公开(公告)号：US11237447B2
公开(公告)日：2022-02-01
申请号：US16250291
申请日：2019-01-17
申请人： Keiichiroh Yutani , Tomoo Fukuda , Hiroyuki Takahashi , Koh Fujimura , Tohru Yashiro , Takaaki Konno , Noboru Sasa
发明人： Keiichiroh Yutani , Tomoo Fukuda , Hiroyuki Takahashi , Koh Fujimura , Tohru Yashiro , Takaaki Konno , Noboru Sasa
IPC分类号： G02F1/15 , G02F1/153 , G09G3/19 , H04N9/16 , G02F1/1523 , G02F1/1516 , G02F1/1334 , G02F1/155 , E06B9/24 , E06B3/67 , G02C7/10 , G03B7/00 , G02F1/157
摘要： An electrochromic element is provided that includes a first substrate and a second substrate that are arranged to oppose each other, a first transparent electrode that is formed on a surface of the first substrate facing the second substrate, a second transparent electrode that is formed on a surface of the second substrate facing the first substrate, and a coloration layer that is arranged between the first transparent electrode and the second transparent electrode. The coloration layer includes an electrochromic material and an electrolyte, and a pattern or a concentration gradient of the electrochromic material is formed in at least a part of the coloration layer.
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