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公开(公告)号：US07184322B2
公开(公告)日：2007-02-27
申请号：US10985876
申请日：2004-11-12
CPC分类号： G11C5/066
摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.
摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。
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公开(公告)号：US07203113B2
公开(公告)日：2007-04-10
申请号：US11090151
申请日：2005-03-28
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.
摘要翻译： 公开了一种半导体存储装置，其中以这样的方式执行控制，即如果当芯片选择信号从不活动（待机）状态转换到活动状态时不执行刷新操作，则读取或写入访问是 立即执行，并且当芯片选择信号经历从非活动状态转换到活动状态时刷新操作正在进行时，等待发生电路产生用于使读或写访问等待的等待信号。
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公开(公告)号：US20050105380A1
公开(公告)日：2005-05-19
申请号：US10985876
申请日：2004-11-12
IPC分类号： G11C11/407 , G11C5/06 , G11C8/00
CPC分类号： G11C5/066
摘要： A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.
摘要翻译： 半导体存储器件具有用于接收地址信号的n位的一部分或所有地址端之间的公共端子，以及用于输出其位宽为n位或更少的数据信号的数据端，以及用于接收m位的专用地址端 地址信号，其中在读取时，在输入了地址信号的n位之后，通过地址信号输入的m位，通过公共端连续地读出选定页内的多个数据信号 从专用地址终端。
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公开(公告)号：US20050219930A1
公开(公告)日：2005-10-06
申请号：US11090151
申请日：2005-03-28
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C11/409
CPC分类号： G11C11/40615 , G11C11/406 , G11C2211/4067
摘要： Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.
摘要翻译： 公开了一种半导体存储装置，其中以这样的方式执行控制，即如果当芯片选择信号经历从非活动（待机）状态转换到活动状态时不执行刷新操作，则读或写访问是 立即执行，并且当芯片选择信号经历从非活动状态转换到活动状态时刷新操作正在进行时，等待发生电路产生用于使读或写访问等待的等待信号。
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5.发明申请Semiconductor memory device and semiconductor device and semiconductor memory device control method 有权半导体存储器件和半导体器件及半导体存储器件控制方法公开(公告)号：US20050237848A1
公开(公告)日：2005-10-27
申请号：US10507117
申请日：2004-09-10
IPC分类号： H01L21/822 , G11C11/407 , G11C11/4074 , G11C11/4076 , H01L27/04 , H03K5/14 , G11C8/02
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。
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公开(公告)号：US07006401B2
公开(公告)日：2006-02-28
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。 此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求 被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。
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公开(公告)号：US20050041520A1
公开(公告)日：2005-02-24
申请号：US10920249
申请日：2004-08-18
申请人： Hiroyuki Takahashi , Takuya Hirota
发明人： Hiroyuki Takahashi , Takuya Hirota
IPC分类号： G11C8/18 , G11C11/403 , G11C11/406 , G11C11/407 , G11C7/00 , G11C8/00
CPC分类号： G11C11/40603 , G11C8/18 , G11C11/406
摘要： A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.
摘要翻译： 适于避免用于刷新的字线的选择周期与用于读/写的字线的选择周期之间的冲突的半导体存储器件包括包括需要刷新以保持存储的多个存储器单元的单元阵列 用于执行控制的数据和装置，使得当在执行刷新操作的时钟周期之后的时钟周期中输入读/写请求时，单元阵列中的读/写操作被延迟至少一个时钟周期，并且 读/写操作在完成刷新后开始。
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公开(公告)号：US07684270B2
公开(公告)日：2010-03-23
申请号：US11892488
申请日：2007-08-23
IPC分类号： G11C7/02
CPC分类号： G11C11/4094 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C2207/2281
摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.
摘要翻译： 在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间 相对于均衡动作后的配线对的电压的中点电压。 根据本发明的均衡器电路，提供了将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同的并具有第一晶体管（N1）的均衡器电路（50） 连接在第一布线（SAP）和连接在第一布线SAP和第二布线（SAN）之间的第一电源电路（例如，HVDD-Va）和第二晶体管（N2）之间。 均衡器电路50使第一晶体管（N1）导通，然后使第二晶体管（N2）导通。
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公开(公告)号：US07663945B2
公开(公告)日：2010-02-16
申请号：US11907442
申请日：2007-10-12
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。
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10.发明授权Semiconductor memory device and semiconductor device and semiconductor memory device control method 有权半导体存储器件和半导体器件及半导体存储器件控制方法公开(公告)号：US07301830B2
公开(公告)日：2007-11-27
申请号：US10507117
申请日：2004-09-10
IPC分类号： G11C11/4074 , G11C11/4076 , G11C11/4063 , G11C7/22 , G11C8/18 , G11C8/08 , G11C7/12
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译： 电池芯单元及其外围电路由相对低压的电源驱动。 提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。 读出放大器将位线的较高电压电平放大到电源电压。 然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟， 降低所提供的电源电压。
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