公开(公告)号：US20110122681A1

公开(公告)日：2011-05-26

申请号：US13021556

申请日：2011-02-04

申请人： Masanao YAMAOKA ,  Takayuki Kawahara

发明人： Masanao YAMAOKA ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

公开(公告)号：US20100327356A1

公开(公告)日：2010-12-30

申请号：US12875097

申请日：2010-09-02

申请人： Takayuki KAWAHARA ,  Masanao YAMAOKA

发明人： Takayuki KAWAHARA ,  Masanao YAMAOKA

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits. having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

摘要翻译： 本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 逻辑电路中的后门电压。 响应于从块的外部激活块来控制逻辑电路块中的小负载。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

公开(公告)号：US20100065911A1

公开(公告)日：2010-03-18

申请号：US12624272

申请日：2009-11-23

申请人： Masanao YAMAOKA ,  Takayuki KAWAHARA

发明人： Masanao YAMAOKA ,  Takayuki KAWAHARA

IPC分类号： H01L27/12

CPC分类号： G11C11/412

摘要： An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

摘要翻译： 本发明的目的是提供一种降低使用按比例缩小的晶体管的整个低功耗SRAM LSI电路的功耗的技术，并且通过减少亚阈值泄漏电流来增加对存储单元的读和写操作的稳定性 以及从漏极流到基板电极的漏电流。 本发明的另一个目的是提供一种防止存储单元中的晶体管数量增加从而防止单元区域增加的技术。 本发明的另一个目的是提供一种通过控制驱动晶体管的BOX层下的阱的电位来确保由具有BOX层的SOI或FD-SOI晶体管构成的SRAM存储单元的稳定工作的技术。

公开(公告)号：US20110102019A1

公开(公告)日：2011-05-05

申请号：US12987664

申请日：2011-01-10

申请人： Kenichi OSADA ,  Takayuki KAWAHARA ,  Masanao YAMAOKA

发明人： Kenichi OSADA ,  Takayuki KAWAHARA ,  Masanao YAMAOKA

IPC分类号： H01L25/00 ,  H01L27/092 ,  H01L29/772

CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

公开(公告)号：US20110181319A1

公开(公告)日：2011-07-28

申请号：US13081145

申请日：2011-04-06

申请人： Takayuki KAWAHARA ,  Masanao YAMAOKA

发明人： Takayuki KAWAHARA ,  Masanao YAMAOKA

IPC分类号： H03K19/0185

CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

摘要翻译： 本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

公开(公告)号：US20100061169A1

公开(公告)日：2010-03-11

申请号：US12620903

申请日：2009-11-18

申请人： Masanao YAMAOKA ,  Takayuki Kawahara

发明人： Masanao YAMAOKA ,  Takayuki Kawahara

IPC分类号： G11C7/00

CPC分类号： H03K19/0016 ,  G11C11/413

摘要： An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state.A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

摘要翻译： 本发明的目的是提供一种降低驱动电路的泄漏电流的技术，该驱动电路在处于其待机状态时必须保持电位（或信息）的驱动电路。 本发明的半导体集成电路器件包括用于驱动电路块的驱动电路。 该驱动电路由具有不同栅极氧化膜厚度的栅极的双栅极晶体管构成。 当电路块处于其待机状态时，具有较薄栅极氧化膜的双栅极晶体管的栅极截止，并且具有较厚栅极氧化膜的栅极导通。 这种布置允许减少电路块和驱动电路的漏电流，同时允许驱动电路传送或切断电路块的电力。

公开(公告)号：US20080144365A1

公开(公告)日：2008-06-19

申请号：US11943495

申请日：2007-11-20

申请人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US20120195110A1

公开(公告)日：2012-08-02

申请号：US13443511

申请日：2012-04-10

申请人： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

公开(公告)号：US20120120738A1

公开(公告)日：2012-05-17

申请号：US13353949

申请日：2012-01-19

申请人： Masanao YAMAOKA ,  Kenichi OSADA

发明人： Masanao YAMAOKA ,  Kenichi OSADA

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/412

摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

公开(公告)号：US20110133786A1

公开(公告)日：2011-06-09

申请号：US13028212

申请日：2011-02-15

申请人： Masanao YAMAOKA ,  Kenichi OSADA

发明人： Masanao YAMAOKA ,  Kenichi OSADA

IPC分类号： H03K5/00

CPC分类号： H03K19/00346

摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。