-
公开(公告)号：US09318178B2
公开(公告)日：2016-04-19
申请号：US13576913
申请日：2010-02-02
CPC分类号： G11C11/15 , G11C11/16 , G11C11/1653 , G11C11/1657 , G11C11/1675 , G11C11/1693
摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.
摘要翻译： 由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。 然而，从系统侧，由于其非易失性特性，期望具有擦除模式。 此外，擦除操作期望以低功耗高速进行。 因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作 通过将预定数据仅写入存储单元阵列COA来实现。
-
2.发明授权公开(公告)号：US08508283B2
公开(公告)日：2013-08-13
申请号：US13081145
申请日：2011-04-06
申请人： Takayuki Kawahara , Masanao Yamaoka
发明人： Takayuki Kawahara , Masanao Yamaoka
CPC分类号： H01L27/1203 , H01L29/78645 , H01L29/78648
摘要： Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.
摘要翻译： 背栅极电压控制提供了在具有根据电路的工作特性具体使用具有背栅的MOS晶体管的宽温度范围内可操作的高速度和低功耗的LSI。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。
-
3.发明申请公开(公告)号：US20130044537A1
公开(公告)日：2013-02-21
申请号：US13522076
申请日：2011-01-13
CPC分类号： H01L27/228 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/5607 , H01L29/82 , H01L43/08 , H01L43/12
摘要： There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.
摘要翻译： 提供了一种使用自旋注入磁化反转型的磁阻效应元件的磁存储器，其中多值操作是可能的，其制造和操作简单。 优选的目的是通过提供两个或更多个彼此串联电连接的磁阻效应元件来解决，并且根据串联元件中承载的电流的方向选择串联元件之一， 其大小及其电流的顺序用于执行写入操作。 例如，通过将具有相同膜结构的各个磁阻效应元件的平面面积尺寸相互分离来解决，以便区分由相应的磁化反转引起的电阻变化量和相应磁化反转所需的阈值电流值 。
-
公开(公告)号：US20120097912A1
公开(公告)日：2012-04-26
申请号：US13345231
申请日：2012-01-06
IPC分类号： H01L45/00
CPC分类号： H01L47/00 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L2924/0002 , H01L2924/00
摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.
-
公开(公告)号：US08031511B2
公开(公告)日：2011-10-04
申请号：US13024252
申请日：2011-02-09
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2213/79
摘要： At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
摘要翻译： 在例如用于使相变元件处于结晶状态的设定操作（SET）时，将元件熔化所需的电压Vreset的脉冲施加到相变元件，随后将脉冲 的电压Vset低于Vreset，并且是将元件结晶所需要的。 而且，该电压Vset的大小然后根据环境温度而改变，使得随着温度变高（TH），电压Vset的大小较小。 以这种方式，提高了设置操作和用于使元件处于非晶态的复位操作（RESET）之间的写入操作余量。
-
公开(公告)号：US20110103136A1
公开(公告)日：2011-05-05
申请号：US12939069
申请日：2010-11-03
CPC分类号： G11C11/4091 , G11C7/065 , G11C2207/065 , H01L27/10897
摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。
-
公开(公告)号：US20110102019A1
公开(公告)日：2011-05-05
申请号：US12987664
申请日：2011-01-10
IPC分类号： H01L25/00 , H01L27/092 , H01L29/772
CPC分类号： H01L29/78648 , G11C11/412 , H01L21/823878 , H01L21/84 , H01L27/0928 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/4908 , H01L29/78609 , H01L2924/0002 , H01L2924/00
摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.
摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。
-
公开(公告)号：US20090310400A1
公开(公告)日：2009-12-17
申请号：US12545379
申请日：2009-08-21
IPC分类号： G11C11/02
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1675 , H01L27/228
摘要： In MRAM using a spin-transfer torque switching, a sufficient writing operation with a small memory cell is realized, and a reading current is enlarged while a reading disturbance is suppressed. In the case where the free layer of the tunnel magneto-resistance element is located on the side of the bit line, using a PMOS transistor, and in the case where the fixed layer of the tunnel magneto-resistance element is located on the side of the bit line, using an NMOS transistor, an anti-parallel writing in a source grounding operation is performed. The reading and writing operation margin is improved by performing a reading operation in an anti-parallel writing direction.
摘要翻译： 在使用自旋转移转矩切换的MRAM中，实现了具有小存储单元的充分的写入操作，并且在读取干扰被抑制的同时增加读取电流。 在隧道磁阻元件的自由层位于位线一侧的情况下，使用PMOS晶体管，并且在隧道磁阻元件的固定层位于 使用NMOS晶体管的位线执行源极接地操作中的反并联写入。 通过执行反并行写入方向的读取操作来提高读取和写入操作余量。
-
9.发明授权Semiconductor devices utilizing double gated fully depleted silicon on insulator MOS transistors 失效采用双门控全绝缘硅绝缘体MOS晶体管的半导体器件公开(公告)号：US07511558B2
公开(公告)日：2009-03-31
申请号：US11362172
申请日：2006-02-27
申请人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
发明人： Kiyoo Itoh , Ryuta Tsuchiya , Takayuki Kawahara
IPC分类号： H03K3/01
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78648 , H03K19/0027 , H03K19/00384 , H03K19/018585
摘要： A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.
摘要翻译： CMOS电路在低电压实现，低功耗实现，高速实现或小尺寸实现。 在使用背阱由阱控制的FD-SOI MOST的电路中，阱处的电压振幅大于栅极处的输入电压幅度。 或者，电路被修改为使用将动态变化为增强模式和耗尽模式的MOST的电路。
-
公开(公告)号：US07420838B2
公开(公告)日：2008-09-02
申请号：US11844333
申请日：2007-08-23
申请人： Kenichi Osada , Takayuki Kawahara
发明人： Kenichi Osada , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C5/147 , G11C8/08 , G11C13/0028 , G11C2213/79
摘要： To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.
摘要翻译： 为了提高相变元件的可靠性，不应该将不需要的电流流入元件。 因此，本发明的目的是提供一种存储单元，其存储根据由施加的热引起的状态变化的信息以及输入/输出电路，并且关闭字线直到电源电路 被激活。 根据本发明，可以防止对元件的不期望的电流流动，从而可以防止数据破坏。
-
-
-
-
-
-
-
-
-
搜索结果
194 条记录 (耗时 0.028 秒)
