公开(公告)号：US20080144365A1

公开(公告)日：2008-06-19

申请号：US11943495

申请日：2007-11-20

申请人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： In this invention, high manufacturing yield is realized and variations in threshold voltage of each MOS transistor in a CMOS•SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. The threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is respectively programmed into control memories according to the results of determination. The levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS•SRAM are controlled to a predetermined error span. A body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 在本发明中，实现了高制造成品率，并补偿了CMOS.SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据测定结果分别被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS.SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US20110102019A1

公开(公告)日：2011-05-05

申请号：US12987664

申请日：2011-01-10

申请人： Kenichi OSADA ,  Takayuki KAWAHARA ,  Masanao YAMAOKA

发明人： Kenichi OSADA ,  Takayuki KAWAHARA ,  Masanao YAMAOKA

IPC分类号： H01L25/00 ,  H01L27/092 ,  H01L29/772

CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

公开(公告)号：US20080174359A1

公开(公告)日：2008-07-24

申请号：US11942939

申请日：2007-11-20

申请人： Kenichi OSADA ,  Masanao Yamaoka ,  Shigenobu Komatsu

发明人： Kenichi OSADA ,  Masanao Yamaoka ,  Shigenobu Komatsu

IPC分类号： H03K3/01

CPC分类号： H03K19/0008 ,  H03K2217/0018

摘要： A substrate bias technique is used in an active mode enabling a high yield, and an operating consumption power and the fluctuation of a signal delay in signal processing are reduced in the active mode. The additional PMOS and NMOS of the additional capacitance circuit are produced in the same production process as the PMOSs and the NMOSs of the CMOS circuits. The gate capacitance of the additional PMOS is coupled between the power supply wiring and the N well and the gate capacitance of the additional NMOS is coupled between the ground wiring and the P well. The noise on the power supply wiring is transmitted to the N well through the gate capacitance and the noise on the ground wiring is transmitted to the P well through the gate capacitance. The fluctuation of noise on the substrate bias voltage between the source and the well of PMOS and NMOS of the CMOS circuits is reduced.

摘要翻译： 在有源模式中使用基板偏压技术，能够实现高产量，并且在活动模式中降低了操作消耗功率和信号处理中的信号延迟的波动。 附加电容电路的附加PMOS和NMOS在与CMOS电路的PMOS和NMOS的生产过程相同的情况下生产。 附加PMOS的栅极电容耦合在电源布线和N阱之间，附加NMOS的栅极电容耦合在接地布线和P阱之间。 电源线上的噪声通过栅极电容传输到N阱，接地线上的噪声通过栅极电容传输到P阱。 CMOS电路的PMOS和NMOS的源极和阱之间的衬底偏置电压上的噪声波动减小。

公开(公告)号：US20120147662A1

公开(公告)日：2012-06-14

申请号：US13350340

申请日：2012-01-13

申请人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Shigenobu KOMATSU

IPC分类号： G11C11/40

CPC分类号： G11C11/417

摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

公开(公告)号：US20100054049A1

公开(公告)日：2010-03-04

申请号：US12543499

申请日：2009-08-18

申请人： Masanao YAMAOKA ,  Kenichi OSADA

发明人： Masanao YAMAOKA ,  Kenichi OSADA

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/412

摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

公开(公告)号：US20120195110A1

公开(公告)日：2012-08-02

申请号：US13443511

申请日：2012-04-10

申请人： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Kazumasa YANAGISAWA

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C5/148

摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

摘要翻译： 当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗 同时存储数据增加。 因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

公开(公告)号：US20120120738A1

公开(公告)日：2012-05-17

申请号：US13353949

申请日：2012-01-19

申请人： Masanao YAMAOKA ,  Kenichi OSADA

发明人： Masanao YAMAOKA ,  Kenichi OSADA

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C11/412

摘要： The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.

摘要翻译： 半导体器件在用于确定字线激活时间的字线定时信号与参考信号之间进行比较，当比较结果表示读取的低条件时，施加用于放大读取余量的反向栅极偏置 并且当比较结果表示写入余量的低条件时，施加用于扩大写入裕度的反向栅极偏置。 参考信号是根据是否补偿根据字线激活时间（或字线脉冲宽度）而波动的工作裕度，或者根据工艺波动（或阈值电压的变化）来补偿工作裕量波动， 。 通过根据字线脉冲宽度控制背栅极偏压，可以提高根据字线脉冲宽度而波动的工作裕度，以及由于其制造期间的阈值电压的变化而波动的工作裕度。

公开(公告)号：US20110133786A1

公开(公告)日：2011-06-09

申请号：US13028212

申请日：2011-02-15

申请人： Masanao YAMAOKA ,  Kenichi OSADA

发明人： Masanao YAMAOKA ,  Kenichi OSADA

IPC分类号： H03K5/00

CPC分类号： H03K19/00346

摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。

公开(公告)号：US20100008058A1

公开(公告)日：2010-01-14

申请号：US12465764

申请日：2009-05-14

申请人： Makoto SAEN ,  Kenichi OSADA

发明人： Makoto SAEN ,  Kenichi OSADA

IPC分类号： H05K1/14

CPC分类号： H01L25/18 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01094 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Traffic between logic LSIs and memory is increasing year by year and there is demand for increase of capacity of communication between them and reduction of power consumption in the communication. Communication distances between LSIs can be reduced by stacking the LSIs. However, in a simple stack of logic LSIs and memory LSIs, it is difficult to ensure heat dissipation to cope with increasing heat densities and ensure transmission characteristics for fast communication with the outside of the stacked package. Also required is a connection topology that improves the performance of communication among the stacked LSIs while ensuring the versatility of the LSIs. An external-communication LSI, a memory LSI, and a logic LSI are stacked in this order in a semiconductor package and are interconnected by through silicon vias. Output terminals of multiple stacked LSIs are connected to an input terminal of a through silicon via of the stacked memory LSI and input terminals of multiple stacked LSIs are connected to an output terminal of a through silicon via of the stacked memory LSI, thereby directly connecting both of the external-communication LSI and the logic LSI to a wiring line of the memory LSI.

摘要翻译： 逻辑LSI与内存之间的通信量逐年增加，需要增加通信能力，减少通信中的功耗。 可以通过堆叠LSI来降低LSI之间的通信距离。 然而，在逻辑LSI和存储器LSI的简单堆叠中，难以确保散热以应对增加的热密度并确保与堆叠封装的外部快速通信的传输特性。 还需要一种连接拓扑结构，从而提高堆叠LSI之间的通信性能，同时确保LSI的通用性。 外部通信LSI，存储器LSI和逻辑LSI以这种顺序堆叠在半导体封装中，并且通过硅通孔互连。 多层堆叠LSI的输出端子连接到层叠存储器LSI的贯穿硅通孔的输入端子，多层堆叠LSI的输入端子连接到层叠存储器LSI的贯穿硅通孔的输出端子，从而直接连接两个 的外部通信LSI和逻辑LSI连接到存储器LSI的布线。

公开(公告)号：US20090269899A1

公开(公告)日：2009-10-29

申请号：US12457917

申请日：2009-06-25

申请人： Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

发明人： Kenichi OSADA ,  Koichiro ISHIBASHI ,  Yoshikazu SAITOH ,  Akio NISHIDA ,  Masaru NAKAMICHI ,  Naoki KITAI

IPC分类号： H01L21/8244

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.