Layout data verification method, mask pattern verification method and circuit operation verification method
    2.
    发明申请
    Layout data verification method, mask pattern verification method and circuit operation verification method 审中-公开
    布局数据验证方法,掩模图案验证方法和电路操作验证方法

    公开(公告)号:US20050204327A1

    公开(公告)日:2005-09-15

    申请号:US11076939

    申请日:2005-03-11

    CPC分类号: G03F1/70 G03F7/705

    摘要: In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.

    摘要翻译: 在本发明的验证方法中,从掩模图案中提取出导致制造中的问题的缺陷。 掩模图案是通过使用于光刻工艺中的光掩模的掩模图案变形而获得的,以便提供接近所需设计图案的转印图像。 验证方法包括以下步骤:确定光刻工艺中的曝光剂量; 基于所确定的曝光剂量在计算机上模拟光刻工艺; 检查是否获得了所需的设计图案; 并定位故障点并输出结果。