公开(公告)号：US07418583B2

公开(公告)日：2008-08-26

申请号：US11126310

申请日：2005-05-11

申请人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

发明人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

IPC分类号： G06F9/34

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3842

摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

摘要翻译： 检测器检测由至少一个处理器执行的指令之间的地址中的至少一种依赖性，所述检测器被用于检测存在所述至少一种依赖性的可能性，其中如果存在所述至少一种依赖性 事实上，检测器检测到存在至少一种依赖性的可能性，并且如果实际上不存在至少一种依赖性，则检测器可以检测至少一种类型的伪随机 依赖。 检测器具有具有多个条目的执行历史存储单元和用于将存储器访问指令的地址转换为条目号的地址转换器，其中不同的地址可以被转换为相同的条目号。

公开(公告)号：US06970997B2

公开(公告)日：2005-11-29

申请号：US10151819

申请日：2002-05-22

申请人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

发明人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3842

摘要： When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions). If the prediction is “failure”, the speculative execution is canceled and the memory operation instruction is executed later in the program order non-speculatively. Whether the speculative execution of the memory operation instructions has succeeded or failed is judged by detecting the data dependence relationship between the memory operation instructions, and the speculative execution result history table is updated taking the judgment into account.

摘要翻译： 当处理器通过数据依赖性推测执行执行存储器操作指令时，参考存储关于过去的存储器操作指令的推测执行的成功/失败结果的历史信息的推测执行结果历史表，从而参考 预测执行成功或失败。 在预测中，存储器操作指令的目标地址由散列函数电路转换为推测执行结果历史表的条目号（允许存在别名），并且由条目号指定的表的条目是 参考。 如果预测为“成功”，则存储器操作指令以推定性的无序执行（关于指令之间的数据依赖关系）执行。 如果预测为“故障”，则推测性执行被取消，并且以非推测方式在程序顺序中稍后执行存储器操作指令。 通过检测存储器操作指令之间的数据依赖关系来判断存储器操作指令的推测执行是成功还是失败，并且考虑到判断来更新推测执行结果历史表。

公开(公告)号：US20050216705A1

公开(公告)日：2005-09-29

申请号：US11126310

申请日：2005-05-11

申请人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

发明人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3842

摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

摘要翻译： 检测器检测由至少一个处理器执行的指令之间的地址中的至少一种依赖性，所述检测器被用于检测存在所述至少一种依赖性的可能性，其中如果存在所述至少一种依赖性 事实上，检测器检测到存在至少一种依赖性的可能性，并且如果实际上不存在至少一种依赖性，则检测器可以检测至少一种类型的伪随机 依赖。 检测器具有具有多个条目的执行历史存储单元和用于将存储器访问指令的地址转换为条目号的地址转换器，其中不同的地址可以被转换为相同的条目号。

公开(公告)号：US06931514B2

公开(公告)日：2005-08-16

申请号：US09994806

申请日：2001-11-28

申请人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

发明人： Atsufumi Shibayama ,  Satoshi Matsushita ,  Sunao Torii ,  Naoki Nishi

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3834 ,  G06F9/3838 ,  G06F9/3842

摘要： A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

公开(公告)号：US06389446B1

公开(公告)日：2002-05-14

申请号：US08888590

申请日：1997-06-30

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： G06F900

CPC分类号： G06F9/4843 ,  G06F8/45 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3842 ,  G06F9/3851

摘要： A program is divided into several instruction streams, and each of them is executed as a thread. A thread processor executed the thread. The thread generates another thread, but one thread is controlled to make a fork operation at most once. Each thread is terminated in the order of generations. A thread manager may be shared with the several thread processors or be distributed to the several thread processors. The thread manager includes a thread sequencer and a thread status table. The thread status table manages execution status of each thread processor and parent-child relation. The thread sequencer requests a thread generation and permits its termination in accordance with the content of the thread status table. The thread processor can execute a thread speculatively.

摘要翻译： 一个程序分为几个指令流，每个指令流都作为一个线程执行。 线程处理器执行线程。 线程生成另一个线程，但是一个线程被控制为最多执行一次fork操作。 每个线程按照几代人的顺序被终止。 线程管理器可以与多个线程处理器共享，或者被分配给多个线程处理器。 线程管理器包括线程序列器和线程状态表。 线程状态表管理每个线程处理器和父子关系的执行状态。 线程定序器根据线程状态表的内容请求线程生成并允许其终止。 线程处理器可以推测地执行线程。

公开(公告)号：US06330661B1

公开(公告)日：2001-12-11

申请号：US09298978

申请日：1999-04-26

申请人： Sunao Torii

发明人： Sunao Torii

IPC分类号： G06F954

CPC分类号： G06F9/3828 ,  G06F9/384 ,  G06F9/3851

摘要： A register content inheriting system contributes for realization of register content inheriting with a hardware of simple construction in a multithread multi-processor. Respective thread execution units and physical common register are provided. Using a register mapping table, a register number to be made reference to from each program is placed in the physical common register. Only as required in inheriting of register content, a relationship of the register mapping table is updated. Upon inheriting the content of the register, the content of the register mapping table is copied.

摘要翻译： 寄存器内容继承系统有助于实现在多线程多处理器中简单构造的硬件继承的寄存器内容。 提供了各自的线程执行单元和物理通用寄存器。 使用寄存器映射表，将从每个程序引用的寄存器编号放在物理公用寄存器中。 只有在继承寄存器内容时，才会更新寄存器映射表的关系。 继承寄存器的内容后，复制寄存器映射表的内容。

公开(公告)号：US08531963B2

公开(公告)日：2013-09-10

申请号：US12663474

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： H04J3/14

CPC分类号： H04L63/0263 ,  G06F15/7825 ,  H04L63/0218

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 传输侧适配器存储第一传送信息，并且根据第一传送信息控制要从第一内核接收的请求信号的传送。 接收侧适配器存储第二传送信息，并且根据第二传送信息控制要通过互连网络接收到第二核的请求信号的传送。 第一递送信息和第二递送信息被分层设置。

公开(公告)号：US20100332709A1

公开(公告)日：2010-12-30

申请号：US12865781

申请日：2009-02-06

申请人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

发明人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

IPC分类号： G06F12/08 ,  G06F13/38

CPC分类号： G06F3/0644 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

摘要： Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access.

摘要翻译： 提供了一种性能优化系统，可以识别即使高速缓存未命中的数量较小，对性能的影响也很大的情况。 绩效优化系统包括：一个需要的时间测量单元，用于测量与待观察的访问有关的所需时间; 所需时间表保持单元，其保存由存储的多个表项组成的所需时间周期表，所述时间表是通过划分产生的每个分类区域的所需时间段的测量值 基于待观察访问的每种类型的存储区域来存储所需时间段的测量值; 表格条目选择单元，对于构成所需时间表的每个分类区域的多个表条目中的哪个表条目进行选择所需时间段的测量值 时间根据被观察的访问存储; 以及高速缓存未命中观察单元，其检测与所述待观察访问相关联的高速缓存未命中的发生。

公开(公告)号：US08638665B2

公开(公告)日：2014-01-28

申请号：US12935035

申请日：2009-04-30

申请人： Masamichi Takagi ,  Sunao Torii

发明人： Masamichi Takagi ,  Sunao Torii

IPC分类号： G06F11/00

CPC分类号： H04L45/00 ,  H04L45/60 ,  H04L49/109 ,  H04L49/1546 ,  H04L49/251

摘要： A router includes: a flit arrival time management section that records flit arrival time which is the time at which the packet is received for the first time, transmission interval of the packet which are acquired from a control packet transmitted prior to the first transmission of a packet and input and output channels of the control packet and requires a crossbar section for an output channel from which the packet is supposed to be output before the flit arrival time; a switch assignment section that performs arbitration on the output channel request and performs input/output connection relationship setting processing; and a switch assignment verification section that verifies whether a result of the input/output connection relationship setting processing coincides with the actual routing of the packet. The cross bar section performs switching of the arriving packet using a result of the input/output connection relationship processing.

摘要翻译： 路由器包括：飞行到达时间管理部，其记录作为第一次接收分组的时间的飞行到达时间，从在第一次发送之前发送的控制分组获取的分组的发送间隔 分组和控制分组的输入和输出通道，并且需要用于输出通道的横截面部分，在该输出通道之前，应该在该飞行器到达时间之前输出该分组; 开关分配单元，对所述输出通道请求进行仲裁，并进行输入/输出连接关系设定处理; 以及开关分配验证部，其验证输入/输出连接关系设置处理的结果是否与分组的实际路由一致。 横杆部分使用输入/输出连接关系处理的结果来执行到达的分组的切换。

公开(公告)号：US08412867B2

公开(公告)日：2013-04-02

申请号：US12663477

申请日：2008-05-30

申请人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Masamichi Takagi ,  Masaki Uekubo ,  Sunao Torii ,  Masato Edahiro

IPC分类号： G06F13/12 ,  H04L12/56

CPC分类号： G06F15/16 ,  G06F21/50 ,  G06F21/577 ,  H04L29/06

摘要： A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

摘要翻译： 本发明的半导体集成电路包括多个核心，以及包括连接到每个核心的适配器的互连网络以及连接适配器以在它们之间通信的多个路由器。 适配器保持指示从核心接收到的请求信号的传送条件的传送信息，并且根据传送信息控制从核心接收的请求信号的传送。