公开(公告)号：US06953979B1

公开(公告)日：2005-10-11

申请号：US09466934

申请日：1999-12-20

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20050275021A1

公开(公告)日：2005-12-15

申请号：US11197397

申请日：2005-08-05

申请人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的上表面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US07067881B2

公开(公告)日：2006-06-27

申请号：US10754539

申请日：2004-01-12

申请人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

发明人： Takuji Matsumoto ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yuuichi Hirano

IPC分类号： H01L27/01

CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7845

摘要： A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.

摘要翻译： 提供一种半导体器件及其制造方法，其可以适当地避免隔离击穿电压的降低，而不会引起诸如结电容增加的不利影响。 在通过形成凹部（14）使硅层（3）变薄之后形成杂质导入区域（11）。 因此，在位于元件隔离绝缘膜（5）的底部和BOX层（2）的顶面之间的p型硅层（3）的部分中不会注入n型杂质，避免了还原 的隔离击穿电压。 此外，由于杂质引入区域（11）形成为到达BOX层（2）的上表面，所以源极/漏极区域（12）的结电容不增加。

公开(公告)号：US20050156242A1

公开(公告)日：2005-07-21

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US07741679B2

公开(公告)日：2010-06-22

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20080315313A1

公开(公告)日：2008-12-25

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06958266B2

公开(公告)日：2005-10-25

申请号：US10120485

申请日：2002-04-12

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

公开(公告)号：US06646306B2

公开(公告)日：2003-11-11

申请号：US09985020

申请日：2001-11-01

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Hideki Naruoka ,  Nobuyoshi Hattori ,  Shigeto Maegawa ,  Yasuo Yamaguchi ,  Takuji Matsumoto

IPC分类号： H01L2701

CPC分类号： H01L21/76286 ,  H01L21/76264 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458

摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

摘要翻译： 一种防止金属污染的半导体器件以及半导体器件的制造方法。 区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物 多晶硅膜的表面。 多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。

公开(公告)号：US20050037524A1

公开(公告)日：2005-02-17

申请号：US10949451

申请日：2004-09-27

申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

IPC分类号： H01L21/66 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/10 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).