公开(公告)号：US06222225B1

公开(公告)日：2001-04-24

申请号：US09405838

申请日：1999-09-27

申请人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

发明人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.

摘要翻译： 半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管 绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。 在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况 。

公开(公告)号：US06413809B2

公开(公告)日：2002-07-02

申请号：US09800914

申请日：2001-03-08

申请人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

发明人： Takuya Nakamura ,  Naoki Koido ,  Hirohisa Iizuka ,  Kazuhito Narita ,  Seiichi Aritome ,  Fumitaka Arai

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device has a semiconductor substrate, an element isolation insulation film embedded in a trench formed in said semiconductor substrate in a state of protruding from a surface of said semiconductor substrate and a transistor having a gate electrode provided in an area surrounded by said element isolation insulation film on said semiconductor substrate, and containing a gate electrode deposited through a gate insulation film before embedding said element isolation insulation film and an upper edge corner of said element isolation insulation film is selectively recessed. In the thus structured semiconductor device, the upper edge corner of the element isolation insulation film is recessed before the patterning process of the gate electrode, thereby preventing such a situation that a part of the gate electrode remains unetched in the patterning process of the gate electrode.

摘要翻译： 半导体器件具有半导体衬底，在从所述半导体衬底的表面突出的状态下嵌入形成在所述半导体衬底中的沟槽中的元件隔离绝缘膜和设置在由所述元件隔离包围的区域中的栅电极的晶体管 绝缘膜，并且包含在嵌入所述元件隔离绝缘膜之前通过栅极绝缘膜沉积的栅电极，并且所述元件隔离绝缘膜的上边缘角被选择性地凹入。 在这样构成的半导体器件中，元件隔离绝缘膜的上边缘角在栅电极的图案化处理之前是凹进的，从而防止了在栅电极的图案化处理中栅电极的一部分未被蚀刻的情况 。

公开(公告)号：US06462373B2

公开(公告)日：2002-10-08

申请号：US09725564

申请日：2000-11-30

申请人： Kazuhiro Shimizu ,  Riichiro Shirota ,  Naoki Koido ,  Seiichi Aritome ,  Hiroaki Tsunoda ,  Tadashi Iguchi ,  Kazuhito Narita ,  Kunihiro Terasaka ,  Hirohisa Iizuka

发明人： Kazuhiro Shimizu ,  Riichiro Shirota ,  Naoki Koido ,  Seiichi Aritome ,  Hiroaki Tsunoda ,  Tadashi Iguchi ,  Kazuhito Narita ,  Kunihiro Terasaka ,  Hirohisa Iizuka

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534

摘要： In a nonvolatile semiconductor memory device, a charge accumulation layer is formed between adjacent two device isolation regions, at least a portion of the charge accumulation layer sandwiched with the device isolation regions has side walls each having a taper angle of 80 degrees or more and less than 90 degrees so that the charge accumulation layer at a lower end has a width wider than that at an upper end, a size of an opening of each of the device isolation regions is 0.25 &mgr;m or less, and a gate length of a memory cell is 0.2 &mgr;m or less.

摘要翻译： 在非易失性半导体存储器件中，在相邻的两个器件隔离区域之间形成电荷累积层，夹在器件隔离区域的电荷累积层的至少一部分具有各自具有80度以上的锥角的侧壁 使得下端的电荷累积层的宽度比上端的宽度宽，器件隔离区域的开口尺寸为0.25μm以下，存储单元的栅极长度 为0.2μm以下。

公开(公告)号：US08259494B2

公开(公告)日：2012-09-04

申请号：US12855507

申请日：2010-08-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

公开(公告)号：US20060120130A1

公开(公告)日：2006-06-08

申请号：US11330352

申请日：2006-01-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US06340611B1

公开(公告)日：2002-01-22

申请号：US09628278

申请日：2000-07-28

申请人： Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshiharu Watanabe ,  Kazuhito Narita

发明人： Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshiharu Watanabe ,  Kazuhito Narita

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to bridge a gap between the two adjacent ones of element isolating regions.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，设置在半导体衬底中的元件隔离区，由元件隔离区中的两个相邻元件隔离区限定的第一元件区和形成在元件区中的存储单元晶体管， 的存储单元晶体管包括形成在对应的一个元件隔离区域上的第一栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极，形成在浮置栅电极上的第二栅极绝缘膜和形成的控制电极 在第二栅极绝缘膜上并且共同连接到特定数量的存储单元晶体管中以用作字线，并且浮置栅极包括第一导电构件，其侧面与两个相邻侧的端部接触 和与第一导电膜电连接的第二导电部件 并且形成为跨越两个相邻的元件隔离区域之间的间隙。

公开(公告)号：US20100309723A1

公开(公告)日：2010-12-09

申请号：US12855507

申请日：2010-08-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

公开(公告)号：US07787277B2

公开(公告)日：2010-08-31

申请号：US12052882

申请日：2008-03-21

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US06836444B2

公开(公告)日：2004-12-28

申请号：US10452128

申请日：2003-06-03

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C1100

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.

摘要翻译： 半导体存储器件包括存储单元阵列，其包括以阵列形式布置的存储单元单元，第一块包括每个具有至少一个存储单元和至少一个选择栅极晶体管的第一存储单元单元，以及包括第二存储单元单元的第二块 具有至少一个存储单元和至少一个选择栅晶体管，其中所述第一块布置在所述存储单元阵列的两端部分上，所述第二块布置在另一部分中，并且所述第一存储单元单元的结构 存储单元阵列的端部与第二存储单元单元的结构不同。

公开(公告)号：US06611447B2

公开(公告)日：2003-08-26

申请号：US10166779

申请日：2002-06-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array and realizing an inexpensive chip having high operation reliability and high manufacturing yield is provided. A first block is constructed by first memory cell units each having a plurality of memory cells connected, a second block is constructed by second memory cell units each having a plurality of memory cells connected, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. By use of the semiconductor memory device, occurrence of a defect caused by a lowering in the etching precision in an end area of the memory cell array can be prevented, and the manufacturing yield can be made high and the operation reliability can be made high without substantially increasing the chip size.