公开(公告)号：US20110027958A1

公开(公告)日：2011-02-03

申请号：US12904809

申请日：2010-10-14

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US08841192B2

公开(公告)日：2014-09-23

申请号：US13444715

申请日：2012-04-11

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US20070296052A1

公开(公告)日：2007-12-27

申请号：US11474670

申请日：2006-06-26

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L27/095

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US20120196420A1

公开(公告)日：2012-08-02

申请号：US13444715

申请日：2012-04-11

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US08173540B2

公开(公告)日：2012-05-08

申请号：US12904809

申请日：2010-10-14

申请人： Tan-Chen Lee ,  Bor-Wen Chan

发明人： Tan-Chen Lee ,  Bor-Wen Chan

IPC分类号： H01L21/4763

CPC分类号： H01L29/456 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66606 ,  H01L29/7833 ,  H01L2924/0002

摘要： A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.

摘要翻译： 提供了具有改进的滚降电阻率和可靠性的半导体器件。 半导体器件包括覆盖半导体衬底的栅极电介质，覆盖栅极电介质的栅极电极，栅电极上的栅极硅化物区域，与栅极电介质相邻的源极/漏极区域，以及源极/漏极硅化物区域， 漏极区域，其中源极/漏极硅化物区域和栅极硅化物区域具有不同的金属组成。

公开(公告)号：US20060292770A1

公开(公告)日：2006-12-28

申请号：US11290914

申请日：2005-11-30

申请人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

发明人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

IPC分类号： H01L21/337 ,  H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

摘要翻译： 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。

公开(公告)号：US20050272215A1

公开(公告)日：2005-12-08

申请号：US11075140

申请日：2005-03-07

申请人： Tan-Chen Lee

发明人： Tan-Chen Lee

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7834

摘要： Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two cycle anneal process during silicide formation, an excess nickel process to transform NiSi2 to NiSi.

摘要翻译： 减少硅中的应力以增强形成在其上的镍单硅化物膜的形成的方法包括应变补偿源极/漏极注入工艺，非晶硅层上的硅化物形成工艺，应变补偿埋层工艺，应变补偿电介质封盖 硅化物形成过程中的层间工艺，硅化物形成期间的二周期退火工艺，将NiSi 2 Ni转变成NiSi的过量镍工艺。

公开(公告)号：US07732298B2

公开(公告)日：2010-06-08

申请号：US11669870

申请日：2007-01-31

申请人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

发明人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/665

摘要： Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

摘要翻译： 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US07253071B2

公开(公告)日：2007-08-07

申请号：US11075140

申请日：2005-03-07

申请人： Tan-Chen Lee

发明人： Tan-Chen Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/26506 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7834

摘要： Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two cycle anneal process during silicide formation, an excess nickel process to transform NiSi2 to NiSi.

摘要翻译： 减少硅中的应力以增强形成在其上的镍单硅化物膜的形成的方法包括应变补偿源极/漏极注入工艺，非晶硅层上的硅化物形成工艺，应变补偿埋层工艺，应变补偿电介质封盖 硅化物形成过程中的层间工艺，硅化物形成期间的二周期退火工艺，将NiSi 2 Ni转变成NiSi的过量镍工艺。

公开(公告)号：US07432149B2

公开(公告)日：2008-10-07

申请号：US11290914

申请日：2005-11-30

申请人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

发明人： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

摘要翻译： 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。