公开(公告)号：US07732298B2

公开(公告)日：2010-06-08

申请号：US11669870

申请日：2007-01-31

申请人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

发明人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/665

摘要： Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

摘要翻译： 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US20080179689A1

公开(公告)日：2008-07-31

申请号：US11669870

申请日：2007-01-31

申请人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

发明人： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC分类号： H01L29/78 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/76829 ,  H01L29/665

摘要： Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

摘要翻译： 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。

公开(公告)号：US11038056B2

公开(公告)日：2021-06-15

申请号：US13371169

申请日：2012-02-10

申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20

摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

公开(公告)号：US08644904B2

公开(公告)日：2014-02-04

申请号：US12488987

申请日：2009-06-22

申请人： Cheng-Hung Chang ,  Yi-Shiang Ouyang ,  Wen-Ying Chang

发明人： Cheng-Hung Chang ,  Yi-Shiang Ouyang ,  Wen-Ying Chang

IPC分类号： A61B5/04 ,  A61N1/00

CPC分类号： C25D5/56 ,  A61B5/0408

摘要： A flexible dry electrode and the manufacturing method thereof are provided. The electrode has an electroplated uneven surface and at least one hole and is made of porous material.

摘要翻译： 提供柔性干电极及其制造方法。 电极具有电镀不平坦表面和至少一个孔，并由多孔材料制成。

公开(公告)号：US20120025313A1

公开(公告)日：2012-02-02

申请号：US13272994

申请日：2011-10-13

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L27/12 ,  H01L29/02

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US08093883B2

公开(公告)日：2012-01-10

申请号：US12246982

申请日：2008-10-07

申请人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chien-Kuo Ko ,  Chi-Chun Yao

发明人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chien-Kuo Ko ,  Chi-Chun Yao

IPC分类号： G01N27/00

CPC分类号： H01J37/3171 ,  H01J37/244 ,  H01J2237/022 ,  H01J2237/24405 ,  H01J2237/24564

摘要： The invention provides an ion current measurement device for a tool having an ion source. The ion current measurement device comprises an ion collecting cup and a replaceable liner. The ion collecting cup is disposed in the tool and the ion collecting cup possesses a cup opening facing the ion source. The replaceable liner is disposed in the ion collecting cup and the replaceable liner entirely covers a continuous inner sidewall of the ion collecting cup.

摘要翻译： 本发明提供了一种用于具有离子源的工具的离子电流测量装置。 离子电流测量装置包括离子收集杯和可更换衬垫。 离子收集杯设置在工具中，离子收集杯具有面向离子源的杯形开口。 可替换的衬垫设置在离子收集杯中，并且可替换的衬套完全覆盖离子收集杯的连续的内侧壁。

公开(公告)号：US08048723B2

公开(公告)日：2011-11-01

申请号：US12329279

申请日：2008-12-05

申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC分类号： H01L21/332

CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20090278196A1

公开(公告)日：2009-11-12

申请号：US12116074

申请日：2008-05-06

申请人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

发明人： Cheng-Hung Chang ,  Chen-Hua Yu ,  Chen-Nan Yeh

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L29/1083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

摘要翻译： 半导体结构包括半导体衬底; 在所述半导体衬底的第一部分上的平面晶体管，其中所述半导体衬底的所述第一部分具有第一顶表面; 以及在半导体衬底的第二部分上的多栅极晶体管。 半导体衬底的第二部分从第一顶表面凹入以形成多栅晶体管的鳍。 翅片通过绝缘体与半导体衬底电隔离。

公开(公告)号：US20080265184A1

公开(公告)日：2008-10-30

申请号：US11742400

申请日：2007-04-30

申请人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chih-Ming Yang ,  Chien-Kuo Ko

发明人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Jung Chen ,  Chih-Ming Yang ,  Chien-Kuo Ko

IPC分类号： G21F3/00

CPC分类号： G21F1/12

摘要： An ion beam blocking component suitable for blocking an ion beam generated by an ion source of an ion implanter is provided. The blocking component includes a front plate, a back plate, and a plurality of side plates. The front plate has at least one opening. The back plate is behind the front plate, and has a plurality of grooves formed on one surface thereof facing the front plate. The side plates are connected between the front plate and the back plate, and a receiving space is formed between these plates.

摘要翻译： 提供了适合于阻挡由离子注入机的离子源产生的离子束的离子束阻挡元件。 阻挡部件包括前板，后板和多个侧板。 前板具有至少一个开口。 背板位于前板的后面，并且在其面向前板的一个表面上形成有多个槽。 侧板连接在前板和后板之间，并且在这些板之间形成容纳空间。

公开(公告)号：US07199383B2

公开(公告)日：2007-04-03

申请号：US11161995

申请日：2005-08-25

申请人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Shih Shen ,  Chung-Jung Chen

发明人： Jui-Fang Chen ,  Cheng-Hung Chang ,  Chung-Shih Shen ,  Chung-Jung Chen

IPC分类号： H01J37/317 ,  H01J37/08 ,  G21G5/00 ,  A21N5/00

CPC分类号： H01J37/3171 ,  H01J37/045 ,  H01J2237/022 ,  H01J2237/24507 ,  H01J2237/24535

摘要： A method for reducing particles during ion implantation is provided. The method involves the use of an improved Faraday flag including a beam plate having thereon a beam striking zone comprising a recessed trench pattern on which the ion beam scans to and fro. An ion beam selected from the mass analyzer is blocked by the Faraday flag in a closed position between the mass analyzer and the semiconductor wafer. A beam current of the ion beam impinging on the beam striking zone of the beam plate is measured. After the beam current measurement, the Faraday flag is removed such that the ion beam impinges on the semiconductor wafer.

摘要翻译： 提供了离子注入期间减少颗粒的方法。 该方法包括使用改进的法拉第标志，其包括其上具有射束冲击区的梁板，该射束板包括凹陷沟槽图案，离子束在其上来回扫描。 在质量分析器和半导体晶片之间的关闭位置，选自质量分析器的离子束被法拉第标志阻挡。 测量入射在梁板的射束区上的离子束的束流。 在束电流测量之后，去除法拉第标记，使得离子束照射在半导体晶片上。