公开(公告)号：US06576934B2

公开(公告)日：2003-06-10

申请号：US10278135

申请日：2002-10-22

Applicant: Tao Cheng ,  Jian-Hsing Lee

Inventor： Tao Cheng ,  Jian-Hsing Lee

IPC: H01L2974

CPC classification number: H01L27/0262

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract translation: 通过在漏极侧和漏极的一部分插入p +扩散和n阱，形成嵌入式SCR，与栅极NMOS相结合，用于保护芯片输入或输出焊盘免受ESD影响，形成低触发， 高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

Abstract translation: 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

公开(公告)号：US06492208B1

公开(公告)日：2002-12-10

申请号：US09671214

申请日：2000-09-28

Applicant: Tao Cheng ,  Jian-Hsing Lee

Inventor： Tao Cheng ,  Jian-Hsing Lee

IPC: H01L21332

CPC classification number: H01L27/0262

Abstract: An embedded parasitic silicon controlled rectifier (SCR) in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from electrostatic discharge ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract translation: 通过在漏极侧插入p +扩散和n阱，创建了一个与门极NMOS相结合的嵌入式寄生可控硅整流器（SCR），用于保护芯片输入或输出焊盘免受静电放电ESD的影响。 漏极形成低触发，高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06611028B2

公开(公告)日：2003-08-26

申请号：US10266661

申请日：2002-10-08

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

公开(公告)号：USD965363S1

公开(公告)日：2022-10-04

申请号：US29819409

申请日：2021-12-15

Applicant: Tao Cheng

Designer： Tao Cheng

公开(公告)号：US09379059B2

公开(公告)日：2016-06-28

申请号：US13286231

申请日：2011-11-01

Applicant: Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Ta-Hsi Chou ,  Peng-Cheng Kao ,  Ling-Wei Ke

IPC: H01L27/10 ,  H01L23/528 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Abstract translation: 集成电路芯片包括其上具有多个IMD层和多个第一导电层的半导体衬底; 覆盖所述多个IMD层和所述第一导电层的第一钝化层; 在覆盖所述第一绝缘层的第一铝层中的至少第一电源/接地网布线; 以及覆盖在第一铝层上的第二铝层中的至少第二电源/接地网布线。

公开(公告)号：US08745019B2

公开(公告)日：2014-06-03

申请号：US13487260

申请日：2012-06-04

Applicant: Tao Cheng ,  Kaushik Chakrabarti ,  Surajit Chaudhuri ,  Dong Xin

Inventor： Tao Cheng ,  Kaushik Chakrabarti ,  Surajit Chaudhuri ,  Dong Xin

IPC: G06F17/30

CPC classification number: G06F17/30672

Abstract: A similarity analysis framework is described herein which leverages two or more similarity analysis functions to generate synonyms for an entity reference string re. The functions are selected such that the synonyms that are generated by the framework satisfy a core set of synonym-related properties. The functions operate by leveraging query log data. One similarity analysis function takes into consideration the strength of similarity between a particular candidate string se and an entity reference string re even in the presence of sparse query log data, while another function takes into account the classes of se and re. The framework also provides indexing mechanisms that expedite its computations. The framework also provides a reduction module for converting long entity reference strings into shorter strings, where each shorter string (if found) contains a subset of the terms in its longer counterpart.

Abstract translation: 本文描述了相似性分析框架，其利用两个或多个相似性分析功能来生成实体参考字符串re的同义词。 选择这些功能使得由框架生成的同义词满足同义词相关属性的核心集合。 这些功能通过利用查询日志数据进行操作。 一个相似性分析功能考虑到即使在存在稀疏查询日志数据的情况下，特定候选字符串se和实体引用字符串之间的相似度的强度，而另一个函数考虑了se和re的类别。 该框架还提供了加速其计算的索引机制。 该框架还提供了一个缩减模块，用于将长实体引用字符串转换为较短的字符串，其中每个较短的字符串（如果找到）包含其较长对应项中的术语的子集。

公开(公告)号：US08587056B2

公开(公告)日：2013-11-19

申请号：US13419443

申请日：2012-03-14

Applicant: Ming-Cheng Lee ,  Tao Cheng ,  Ming-Tzong Yang

Inventor： Ming-Cheng Lee ,  Tao Cheng ,  Ming-Tzong Yang

IPC: H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/7833 ,  H01L29/7835

Abstract: A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

Abstract translation: 高压MOS晶体管包括覆盖半导体衬底的有源区的栅极; 漏极掺杂区域从栅极的边缘拉回距离L; 在栅极和漏极掺杂区域之间的第一轻掺杂区域; 第一离子阱中的源极掺杂区; 以及在栅极和源极掺杂区域之间的第二轻掺杂区域。

公开(公告)号：US08120067B1

公开(公告)日：2012-02-21

申请号：US13281458

申请日：2011-10-26

Applicant: Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

Inventor： Ching-Chung Ko ,  Tao Cheng ,  Tien-Yueh Liu ,  Dar-Shii Chou ,  Peng-Cheng Kao

IPC: H01L27/10

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first power/ground mesh wiring lines, in a second conductive layer overlying the first insulating layer, for distributing power signal or ground signal; and a second insulating layer covering the second conductive layer and the first insulating layer.

Abstract translation: 集成电路芯片包括其上具有多个IMD层的半导体衬底和嵌入IMD层中的第一导电层; 覆盖IMD层和第一导电层的第一绝缘层; 多个第一电源/接地网状布线，位于覆盖所述第一绝缘层的第二导电层中，用于分配电力信号或接地信号; 以及覆盖所述第二导电层和所述第一绝缘层的第二绝缘层。

公开(公告)号：US08088622B2

公开(公告)日：2012-01-03

申请号：US12331117

申请日：2008-12-09

Applicant: David T. Scadden ,  Tao Cheng

Inventor： David T. Scadden ,  Tao Cheng

IPC: C12N15/87

CPC classification number: C12N5/0647 ,  A01K2217/05 ,  A61K48/00 ,  A61K2035/124 ,  C07K2319/00 ,  C12N2501/125 ,  C12N2501/145 ,  C12N2501/23 ,  C12N2501/26 ,  C12N2501/405

Abstract: The expansion of a population of stem cells or progenitor cells, or precursors thereof, may be accomplished by disrupting or inhibiting p21cip1/waf1 and/or p27, cyclin dependent kinase inhibitors. In the absence of p27 activity, progenitor cells move into the cell cycle and proliferate; whereas in the absence of p21 activity, stem cells move into the cell cycle and proliferate without losing their pluripotentiality (i.e., their ability to differentiate into the various cell lines found in the blood stream). Any type of stem cell or progenitor cell, or precursor thereof, including, but not limited to, hematopoietic, gastrointestinal, lung, neural, skin, muscle, cardiac muscle, renal, mesenchymal, embryonic, fetal, or liver cell may be used in accordance with the invention. The present invention provides a method of expanding a cell population, cells with decreased p27 and/or p21 activity, transgenic animals with a disrupted p27 and/or p21 gene, pharmaceutical compositions comprising the cells of the invention, and methods of using these cells in gene therapy (e.g., stem cell gene therapy) and bone marrow transplantation.

Abstract translation: 干细胞或祖细胞群或其前体的扩增可以通过破坏或抑制p21cip1 / waf1和/或p27细胞周期蛋白依赖性激酶抑制剂来实现。 在没有p27活性的情况下，祖细胞进入细胞周期并增殖; 而在没有p21活性的情况下，干细胞进入细胞周期并增殖而不丧失其多能性（即，它们分化成血液中发现的各种细胞系的能力）。 包括但不限于造血，胃肠，肺，神经，皮肤，肌肉，心肌，肾，间充质，胚胎，胎儿或肝细胞的任何类型的干细胞或祖细胞或其前体可用于 根据本发明。 本发明提供了扩增细胞群的方法，具有降低的p27和/或p21活性的细胞，具有破坏的p27和/或p21基因的转基因动物，包含本发明细胞的药物组合物，以及使用这些细胞的方法 基因治疗（如干细胞基因治疗）和骨髓移植。