公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

申请人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

发明人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

摘要翻译： 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

公开(公告)号：US06611028B2

公开(公告)日：2003-08-26

申请号：US10266661

申请日：2002-10-08

申请人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

发明人： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

公开(公告)号：US06576934B2

公开(公告)日：2003-06-10

申请号：US10278135

申请日：2002-10-22

申请人： Tao Cheng ,  Jian-Hsing Lee

发明人： Tao Cheng ,  Jian-Hsing Lee

IPC分类号： H01L2974

CPC分类号： H01L27/0262

摘要： An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

摘要翻译： 通过在漏极侧和漏极的一部分插入p +扩散和n阱，形成嵌入式SCR，与栅极NMOS相结合，用于保护芯片输入或输出焊盘免受ESD影响，形成低触发， 高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US06492208B1

公开(公告)日：2002-12-10

申请号：US09671214

申请日：2000-09-28

申请人： Tao Cheng ,  Jian-Hsing Lee

发明人： Tao Cheng ,  Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262

摘要： An embedded parasitic silicon controlled rectifier (SCR) in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from electrostatic discharge ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

摘要翻译： 通过在漏极侧插入p +扩散和n阱，创建了一个与门极NMOS相结合的嵌入式寄生可控硅整流器（SCR），用于保护芯片输入或输出焊盘免受静电放电ESD的影响。 漏极形成低触发，高效SCR。 器件布局使得漏极连接在p +扩散和n +漏极紧密连接在一起，使得该连接非常短，从而防止闩锁。 寄生SCR完全包含在结构两侧的n +扩散（接地栅极NMOS晶体管的源极）内，因此被称为嵌入式SCR。 对于12伏I / O设备，两个n +漏极中的每一个都放置在跨越n-阱一半的其自身的n型掺杂漏极（ndd）区域中。 根据需要重复该结构，并且在两个周边注入p +扩散并连接到最近的n +源和参考电压。

公开(公告)号：US08378422B2

公开(公告)日：2013-02-19

申请号：US12609803

申请日：2009-10-30

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC分类号： H01L23/62 ,  H01L29/72 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

摘要： Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

摘要翻译： 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US08344416B2

公开(公告)日：2013-01-01

申请号：US12777672

申请日：2010-05-11

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

公开(公告)号：US08288822B2

公开(公告)日：2012-10-16

申请号：US13172555

申请日：2011-06-29

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC分类号： H01L27/06

CPC分类号： H01L27/0259 ,  H01L27/1203

摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

公开(公告)号：US20110254091A1

公开(公告)日：2011-10-20

申请号：US13172555

申请日：2011-06-29

申请人： Jiaw-Ren Shih ,  Jian-Hsing Lee

发明人： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC分类号： H01L27/12

CPC分类号： H01L27/0259 ,  H01L27/1203

摘要： An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

摘要翻译： 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

公开(公告)号：US20090101937A1

公开(公告)日：2009-04-23

申请号：US12342294

申请日：2008-12-23

申请人： Jian-Hsing Lee ,  Shui-Hunyi Chen

发明人： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC分类号： H01L29/73

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07420250B2

公开(公告)日：2008-09-02

申请号：US11212000

申请日：2005-08-25

申请人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

发明人： Shu-Chuan Lee ,  Ming-Hsiang Song ,  Shao-Chang Huang ,  Yi-Hsun Wu ,  Kuo-Feng Yu ,  Jian-Hsing Lee ,  Tong-Chern Ong

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.

摘要翻译： 提供一种静电放电（ESD）保护装置及其制造方法。 在一个示例中，ESD保护装置包括形成在衬底中的齐纳二极管区域和邻近齐纳二极管区域形成的N型金属氧化物半导体（NMOS）器件。 齐纳二极管区域具有两个掺杂区域，位于两个掺杂区域之间的接地电位的栅极和在衬底中形成的两个光掺杂漏极（LDD）特征。 LDD特征之一位于两个掺杂区域和栅极之间。 NMOS器件包括形成在衬底中的源极和漏极，以及位于源极和漏极之间的第二栅极。